Gate leakage reduction for scaled devices using transistor stacking. - Saibal Mukhopadhyay; Cassondra Neau; R. T. Cakici; Amit Agarwal 001; Chris H. Kim; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. - Animesh Datta; Ashish Goel; R. T. Cakici; Hamid Mahmoodi; Dheepa Lekshmanan; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)