Architectural Verification of Processors Using Symbolic Instruction Graphs. - Ashok K. Chandra; Vijay S. Iyengar; R. V. Jawalekar; Michael P. Mullen; Indira Nair; Barry K. Rosen (ICCD, 1994)

AVPGEN-A test generator for architecture verification. - Ashok K. Chandra; Vijay S. Iyengar; D. Jameson; R. V. Jawalekar; Indira Nair; Barry K. Rosen; Michael P. Mullen; J. Yoon; R. Armoni; Daniel Geist; Yaron Wolfsthal (IEEE Trans. Very Large Scale Integr. Syst., 1995)