Energy delay analysis of partial product reduction methods for parallel multiplier implementation. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1996)

A Low Power Approach to Floating Point Adder Design. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ICCD, 1997)

Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1997)

A Low Power Floating Point Accumulator. - R. V. K. Pillai; Asim J. Al-Khalili; Dhamin Al-Khalili (VLSI Design, 1998)

An IEEE Compliant Floating Point MAF. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (VLSI, 1999)

Power implications of precision limited arithmetic in floating point FIR filters. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISCAS (1), 1999)

Low power floating point MAFs-a comparative study. - R. V. K. Pillai; S. Y. A. Shah; A. J. Al-Khalili; Dhamin Al-Khalili (ISSPA, 2001)

A Low Power Approach to Floating Point Adder Design for DSP Applications. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili; S. Y. A. Shah (J. VLSI Signal Process., 2001)