Ensuring On-Die Power Supply Robustness in High-Performance Designs. - Sreekanth Soman; Amit Brahme; Ramakrishnan Venkatraman; Raashid Shaikh; Santhosh Thiyagaraja; Mahendrasing Patil (VLSI Design, 2011)

At-speed capture power reduction using layout-aware granular clock gate enable controls. - Raashid Shaikh; Pradeep Wilson; Khushboo Agarwal; H. V. Sanjay; Rajesh Tiwari; Kaushik Lath; Srivaths Ravi 001 (ITC, 2014)