An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter. - Reza Lotfi; Rabeeh Majidi; Mohammad Maymandi-Nejad; Wouter A. Serdijn (ISCAS, 2009)

Digital background calibration of redundant split-flash ADC in 45nm CMOS. - Rabeeh Majidi; Anthony Crasso; John A. McNeill (ISCAS, 2012)

Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC sample clock synthesis. - John A. McNeill; Jianping Gong; Rabeeh Majidi (MWSCAS, 2013)

Lookup-table-based background linearization for VCO-based ADCs. - John A. McNeill; Rabeeh Majidi; Jianping Gong; Chengxin Liu (CICC, 2014)

"Split ADC" Background Linearization of VCO-Based ADCs. - John A. McNeill; Rabeeh Majidi; Jianping Gong (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)