Fault Simulation in a Distributed Environment. - Patrick A. Duba; Rabindra K. Roy; Jacob A. Abraham; William A. Rogers (DAC, 1988)

Compaction of ATPG-generated test sequences for sequential circuits. - Rabindra K. Roy; Thomas M. Niermann; Janak H. Patel; Jacob A. Abraham; Resve A. Saleh (ICCAD, 1988)

Timing verification and synthesis of circuits for delay fault testability - Rabindra K. Roy (1990)

The Best Flip-Flops to Scan. - Miron Abramovici; James J. Kulikowski; Rabindra K. Roy (ITC, 1991)

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. - Abhijit Chatterjee; Rabindra K. Roy; Jacob A. Abraham; Janak H. Patel (Digit. Signal Process., 1991)

Automatic test generation for linear digital systems with bi-level search using matrix transform methods. - Rabindra K. Roy; Abhijit Chatterjee; Janak H. Patel; Jacob A. Abraham; Manuel A. d'Abreu (ICCAD, 1992)

Delay fault testing of iterative arithmetic arrays. - Rabindra K. Roy; Naveena Nagi; Abhijit Chatterjee; Manuel A. d'Abreu (VTS, 1992)

Dynamic redundancy identification in automatic test generation. - Miron Abramovici; David T. Miller; Rabindra K. Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Test compaction for sequential circuits. - Thomas M. Niermann; Rabindra K. Roy; Janak H. Patel; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. - Abhijit Chatterjee; Rabindra K. Roy (DAC, 1993)

Exploiting hardware sharing in high-level synthesis for partial scan optimization. - Sujit Dey; Miodrag Potkonjak; Rabindra K. Roy (ICCAD, 1993)

Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. - Abhijit Chatterjee; Rabindra K. Roy (ICCD, 1993)

Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. - Abhijit Chatterjee; Rabindra K. Roy; Manuel A. d'Abreu (VLSI Design, 1993)

Greedy hardware optimization for linear digital circuits using number splitting and refactorization. - Abhijit Chatterjee; Rabindra K. Roy; Manuel A. d'Abreu (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Signal Transition Graph Transformations for Initializability. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar; Dhiraj K. Pradhan (EDAC-ETC-EUROASIC, 1994)

Behavioral synthesis of low-cost partial scan designs for DSP applications. - Sujit Dey; Miodrag Potkonjak; Rabindra K. Roy (ICASSP (2), 1994)

Initialization Isuues in the Synthesis of Asynchronous Circuits. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar; Dhiraj K. Pradhan (ICCD, 1994)

Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. - Abhijit Chatterjee; Rabindra K. Roy (VLSI Design, 1994)

Design for diagnosability of linear digital filters using time-space expansion. - Abhijit Chatterjee; Rabindra K. Roy (VTS, 1994)

Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. - Sujit Dey; Miodrag Potkonjak; Rabindra K. Roy (VTS, 1994)

Guest Editor's Introduction: Practical Asynchronous Design. - Tam-Anh Chu; Rabindra K. Roy (IEEE Des. Test Comput., 1994)

Synthesis-for-testability using transformations. - Miodrag Potkonjak; Sujit Dey; Rabindra K. Roy (ASP-DAC, 1995)

Advantages of High-Level Test Synthesis over Design for Test. - Rabindra K. Roy (ITC, 1995)

Guest Editors' Introduction: More Practical Asynchronous Design. - Tam-Anh Chu; Rabindra K. Roy (IEEE Des. Test Comput., 1995)

Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. - Miodrag Potkonjak; Sujit Dey; Rabindra K. Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. - Miodrag Potkonjak; Sujit Dey; Rabindra K. Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Synchronous Test Generation Model for Asynchronous Circuits. - Savita Banerjee; Srimat T. Chakradhar; Rabindra K. Roy (VLSI Design, 1996)

Initialization issues in asynchronous circuit synthesis. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar (J. Electron. Test., 1996)

Synthesis of initializable asynchronous circuits. - Srimat T. Chakradhar; Savita Banerjee; Rabindra K. Roy; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Impact of Partial Reset on Fault Independent Testing and BIST. - Huy Nguyen 001; Abhijit Chatterjee; Rabindra K. Roy (VLSI Design, 1997)

T5: Low-Power Design. - Kaushik Roy; Rabindra K. Roy; Ramesh Harjani; K. S. Murthy (VLSI Design, 1997)

Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization. - Abhijit Chatterjee; Rabindra K. Roy (IEEE Trans. Computers, 1997)

Considering Testability during High-level Design (Embedded Tutorial). - Sujit Dey; Anand Raghunathan; Rabindra K. Roy (ASP-DAC, 1998)

Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. - Huy Nguyen 001; Rabindra K. Roy; Abhijit Chatterjee (VLSI Design, 1998)

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. - Srivaths Ravi 001; Indradeep Ghosh; Rabindra K. Roy; Sujit Dey (J. Electron. Test., 1998)

Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. - Huy T. Nguyen; Abhijit Chatterjee; Rabindra K. Roy (J. VLSI Signal Process., 1998)

Characterizing Individual Gate Power Sensitivity in Low Power Design. - Unni Narayanan; Georgios I. Stamoulis; Rabindra K. Roy (VLSI Design, 1999)

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. - Huy Nguyen 001; Rabindra K. Roy; Abhijit Chatterjee (J. Electron. Test., 1999)

EDA challenges facing future microprocessor design. - T. Karn; Shishpal Rawat; Desmond Kirkpatrick; Rabindra K. Roy; Gregory S. Spirakis; Naveed A. Sherwani; Craig Peterson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)