ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist. - Rachel Selina Rajarathnam; Yibo Lin; Yier Jin; David Z. Pan (HOST, 2020)

DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. - Rachel Selina Rajarathnam; Mohamed Baker Alawieh; Zixuan Jiang; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2022)

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. - Rachel Selina Rajarathnam; Zixuan Jiang; Mahesh A. Iyer; David Z. Pan (ISPD, 2023)

DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints. - Zhili Xiong; Rachel Selina Rajarathnam; Zhixing Jiang; Hanqing Zhu; David Z. Pan (CoRR, 2023)

A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs. - Zhili Xiong; Rachel Selina Rajarathnam; David Z. Pan (FCCM, 2024)

Better Together: Combining Analytical and Annealing Methods for FPGA Placement. - Rachel Selina Rajarathnam; Kate Thurmer; Vaughn Betz; Mahesh A. Iyer; David Z. Pan (FPL, 2024)

Automated Physical Design Watermarking Leveraging Graph Neural Networks. - Ruisi Zhang; Rachel Selina Rajarathnam; David Z. Pan; Farinaz Koushanfar (MLCAD, 2024)

ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection. - Ruisi Zhang; Rachel Selina Rajarathnam; David Z. Pan; Farinaz Koushanfar (CoRR, 2024)