A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. - Purushotham Murugappa; Rachid Al-Khayat; Amer Baghdadi; Michel Jézéquel (DATE, 2011)

Area and throughput optimized ASIP for multi-standard turbo decoding. - Rachid Al-Khayat; Purushotham Murugappa; Amer Baghdadi; Michel Jézéquel (International Symposium on Rapid System Prototyping, 2011)

Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm2 multi-standard turbo decoder. - Rachid Al-Khayat; Amer Baghdadi; Michel Jézéquel (ISSoC, 2012)