A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. - Radhika S. Grover; Weijia Shang; Qiang Li (FPL, 2000)

A faster distributed arithmetic architecture for FPGAs. - Radhika S. Grover; Weijia Shang; Qiang Li (FPGA, 2002)

Bit-level two's complement matrix multiplication. - Radhika S. Grover; Weijia Shang; Qiang Li (Integr., 2002)

Providing Statistical QoS Guarantees for Interactive Operations in Parallel Multimedia Servers. - Radhika S. Grover; Qiang Li; George Fegan (PDCS, 2004)

Performance Trade-offs of DCT with Variable Length Carry Chains in FPGAs. - Radhika S. Grover; Shobha Krishnan; Weijia Shang; Qiang Li (PDPTA, 2004)

Performance study of data layout schemes for a SAN-based video server. - Radhika S. Grover; Qiang Li; Hans-Peter Dommel (Parallel Comput., 2008)