An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. - Radoslaw Czarnecki; Stanislaw Deniziak; Krzysztof Sapiecha (DSD, 2003)

Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. - Radoslaw Czarnecki; Stanislaw Deniziak (DDECS, 2007)

Synthesis of Real-Time Applications for Internet of Things. - Slawomir Bak; Radoslaw Czarnecki; Stanislaw Deniziak (ICPCA/SWS, 2012)