Using JIT Compilation and Configurable Runtime Systems for Efficient Deployment of Java Programs on Ubiquitous Devices. - Radu Teodorescu; Raju Pandey (UbiComp, 2001)

Using code collection to support large applications on mobile devices. - Lucian Popa 002; Irina Athanasiu; Costin Raiciu; Raju Pandey; Radu Teodorescu (MobiCom, 2004)

Prototyping Architectural Support for Program Rollback Using FPGAs. - Radu Teodorescu; Josep Torrellas (FCCM, 2005)

Log-based architectures for general-purpose monitoring of deployed code. - Shimin Chen; Babak Falsafi; Phillip B. Gibbons; Michael Kozuch; Todd C. Mowry; Radu Teodorescu; Anastassia Ailamaki; Limor Fix; Gregory R. Ganger; Bin Lin 002; Steven W. Schlosser (ASID, 2006)

SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. - Radu Teodorescu; Jun Nakano; Josep Torrellas (IEEE Micro, 2006)

HARD: Hardware-Assisted Lockset-based Race Detection. - Pin Zhou; Radu Teodorescu; Yuanyuan Zhou (HPCA, 2007)

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. - Radu Teodorescu; Jun Nakano; Abhishek Tiwari 002; Josep Torrellas (MICRO, 2007)

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. - Radu Teodorescu; Josep Torrellas (ISCA, 2008)

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches. - Timothy N. Miller; Renji Thomas; James Dinan; Bruce M. Adcock; Radu Teodorescu (MICRO, 2010)

Flexible Error Protection for Energy Efficient Reliable Architectures. - Timothy N. Miller; Nagarjuna Surapaneni; Radu Teodorescu (SBAC-PAD, 2010)

StVEC: A Vector Instruction Extension for High Performance Stencil Computation. - Naser Sedaghati; Renji Thomas; Louis-Noël Pouchet; Radu Teodorescu; P. Sadayappan (PACT, 2011)

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. - Timothy N. Miller; Xiang Pan; Renji Thomas; Naser Sedaghati; Radu Teodorescu (HPCA, 2012)

VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors. - Timothy N. Miller; Renji Thomas; Xiang Pan; Radu Teodorescu (ISCA, 2012)

Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units. - Timothy N. Miller; Renji Thomas; Radu Teodorescu (IEEE Comput. Archit. Lett., 2012)

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. - Anys Bacha; Radu Teodorescu (ISCA, 2013)

Runtime failure rate targeting for energy-efficient reliability in chip microprocessors. - Timothy N. Miller; Nagarjuna Surapaneni; Radu Teodorescu (Concurr. Comput. Pract. Exp., 2013)

Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors. - Xiang Pan; Radu Teodorescu (PACT, 2014)

NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores. - Xiang Pan; Radu Teodorescu (ICCD, 2014)

Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors. - Anys Bacha; Radu Teodorescu (MICRO, 2014)

On Using the Roofline Model with Lower Bounds on Data Movement. - Venmugil Elango; Naser Sedaghati; Fabrice Rastello; Louis-Noël Pouchet; J. Ramanujam; Radu Teodorescu; P. Sadayappan (ACM Trans. Archit. Code Optim., 2014)

Authenticache: harnessing cache ECC for system authentication. - Anys Bacha; Radu Teodorescu (MICRO, 2015)

Commentary: When the brain takes a break: a model-based analysis of mind wandering. - Vadim Axelrod; Radu Teodorescu (Frontiers Comput. Neurosci., 2015)

Core tunneling: Variation-aware voltage noise mitigation in GPUs. - Renji Thomas; Kristin Barber; Naser Sedaghati; Li Zhou 012; Radu Teodorescu (HPCA, 2016)

EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. - Renji Thomas; Naser Sedaghati; Radu Teodorescu (ISPASS, 2016)

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. - Dimitrios Skarlatos 002; Renji Thomas; Aditya Agrawal; Shibin Qin; Robert C. N. Pilawa-Podgurski; Ulya R. Karpuzcu; Radu Teodorescu; Nam Sung Kim; Josep Torrellas (MICRO, 2016)

One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. - Yuan Xiao 001; Xiaokuan Zhang; Yinqian Zhang; Radu Teodorescu (USENIX Security Symposium, 2016)

Respin: Rethinking Near-Threshold Multiprocessor Design with Non-volatile Memory. - Xiang Pan; Anys Bacha; Radu Teodorescu (IPDPS, 2017)

NVCool: When Non-Volatile Caches Meet Cold Boot Attacks. - Xiang Pan; Anys Bacha; Spencer Rudolph; Li Zhou 012; Yinqian Zhang; Radu Teodorescu (ICCD, 2018)

C-Graph: A Highly Efficient Concurrent Graph Reachability Query Framework. - Li Zhou 012; Ren Chen; Yinglong Xia; Radu Teodorescu (ICPP, 2018)

SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels. - Kristin Barber; Anys Bacha; Li Zhou 012; Yinqian Zhang; Radu Teodorescu (PACT, 2019)

Adaptive parallel execution of deep neural networks on heterogeneous edge devices. - Li Zhou 012; Mohammad Hossein Samavatian; Anys Bacha; Saikat Majumdar; Radu Teodorescu (SEC, 2019)

Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights. - Sobhan Moosavi; Mohammad Hossein Samavatian; Srinivasan Parthasarathy 001; Radu Teodorescu; Rajiv Ramnath (SIGSPATIAL/GIS, 2019)

Distributing Deep Neural Networks with Containerized Partitions at the Edge. - Li Zhou 012; Hao Wen 001; Radu Teodorescu; David H. C. Du (HotEdge, 2019)

Isolating Speculative Data to Prevent Transient Execution Attacks. - Kristin Barber; Anys Bacha; Li Zhou 012; Yinqian Zhang; Radu Teodorescu (IEEE Comput. Archit. Lett., 2019)

A Pattern-Based API for Mapping Applications to a Hierarchy of Multi-Core Devices. - Jia Guo; Radu Teodorescu; Gagan Agrawal (CCGRID, 2020)

SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. - Yuan Xiao 001; Yinqian Zhang; Radu Teodorescu (NDSS, 2020)

RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory. - Mohammad Hossein Samavatian; Anys Bacha; Li Zhou 012; Radu Teodorescu (ACM J. Emerg. Technol. Comput. Syst., 2020)

Fused DSConv: Optimizing Sparse CNN Inference for Execution on Edge Devices. - Jia Guo; Radu Teodorescu; Gagan Agrawal (CCGRID, 2021)

A Fused Inference Design for Pattern-Based Sparse CNN on Edge Devices. - Jia Guo; Radu Teodorescu; Gagan Agrawal (HiPC, 2021)

Using Undervolting as an on-Device Defense Against Adversarial Machine Learning Attacks. - Saikat Majumdar; Mohammad Hossein Samavatian; Kristin Barber; Radu Teodorescu (HOST, 2021)

INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities. - Moein Ghaniyoun; Kristin Barber; Yinqian Zhang; Radu Teodorescu (ISCA, 2021)

HASI: Hardware-Accelerated Stochastic Inference, A Defense Against Adversarial Machine Learning Attacks. - Mohammad Hossein Samavatian; Saikat Majumdar; Kristin Barber; Radu Teodorescu (CoRR, 2021)

Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters. - Saikat Majumdar; Mohammad Hossein Samavatian; Radu Teodorescu (HOST, 2022)

ENCLYZER: Automated Analysis of Transient Data Leaks on Intel SGX. - Jiuqin Zhou; Yuan Xiao 001; Radu Teodorescu; Yinqian Zhang (SEED, 2022)

A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP. - Mengyuan Li 004; Luca Wilke; Jan Wichelmann; Thomas Eisenbarth 001; Radu Teodorescu; Yinqian Zhang (SP, 2022)

A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications. - Kristin Barber; Moein Ghaniyoun; Yinqian Zhang; Radu Teodorescu (IEEE Comput. Archit. Lett., 2022)

DNNShield: Dynamic Randomized Model Sparsification, A Defense Against Adversarial Machine Learning. - Mohammad Hossein Samavatian; Saikat Majumdar; Kristin Barber; Radu Teodorescu (CoRR, 2022)

Special Issue on Top Picks From the 2021 Computer Architecture Conferences. - Sudhanva Gurumurthi; Radu Teodorescu (IEEE Micro, 2022)

TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments. - Moein Ghaniyoun; Kristin Barber; Yuan Xiao 001; Yinqian Zhang; Radu Teodorescu (ISCA, 2023)

Voltage Noise-Based Adversarial Attacks on Machine Learning Inference in Multi-Tenant FPGA Accelerators. - Saikat Majumdar; Radu Teodorescu (HOST, 2024)

MicroSampler: A Framework for Microarchitecture-Level Leakage Detection in Constant Time Execution. - Moein Ghaniyoun; Kristin Barber; Yinqian Zhang; Radu Teodorescu (DSN, 2025)