RAPID-retargetability for reusability of application-driven quadrature D/A interface block design. - José E. Franca; Nuno Horta; M. Pereira; João C. Vital; Rafael Castro-López; Manuel Delgado-Restituto; Francisco V. Fernández 001; Ángel Rodríguez-Vázquez; J. Ramos; P. Santos (ICECS, 1999)

Retargeting of mixed-signal blocks for SoCs. - Rafael Castro-López; Francisco V. Fernández 001; Manuel Delgado-Restituto; Ángel Rodríguez-Vázquez (DATE, 2001)

Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. - Rafael Castro-López; Francisco V. Fernández 001; Fernando Medeiro; Ángel Rodríguez-Vázquez (DATE, 2003)

A 1000FPS@128×128 vision processor with 8-bit digitized I/O. - Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez; Rafael Castro-López; Servando Espejo-Meana (ESSCIRC, 2003)

Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey. - Rafael Castro-López; José M. de la Rosa 001; R. Romay; Rocío del Río; Fernando Medeiro; Francisco V. Fernández 001 (FDL, 2003)

Accurate VHDL-based simulation of Sigma-Delta modulators. - Rafael Castro-López; Francisco V. Fernández 001; Fernando Medeiro; Ángel Rodríguez-Vázquez (ISCAS (4), 2003)

A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. - Jesús Ruiz-Amaya; Manuel Delgado-Restituto; Juan Francisco Fernández-Bootello; Davide Brandano; Rafael Castro-López; José M. de la Rosa 001 (APCCAS, 2006)

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK. - Alonso Morgado; V. J. Rivas; Rocío del Río; Rafael Castro-López; Francisco V. Fernández 001; José M. de la Rosa 001 (Integr., 2008)

An Integrated Layout-Synthesis Approach for Analog ICs. - Rafael Castro-López; Oscar Guerra; Elisenda Roca; Francisco V. Fernández 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Analog layout synthesis - Recent advances in topological approaches. - Helmut Gräb; Florin Balasa; Rafael Castro-López; Yu-Wei Chang 002; Francisco V. Fernández 001; Mark Po-Hung Lin; Martin Strasser (DATE, 2009)

Hierarchical synthesis based on pareto-optimal fronts. - Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (ECCTD, 2009)

Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview. - Elisenda Roca; Mourad Fakhfakh; Rafael Castro-López; Francisco V. Fernández 001 (ICECS, 2009)

AMS/RF-CMOS circuit design for wireless transceivers. - Rafael Castro-López; Delia Rodríguez de Llera; Mohammed Ismail 001; Francisco V. Fernández 001 (Integr., 2009)

Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey. - José M. de la Rosa 001; Rafael Castro-López; Alonso Morgado; Edwin C. Becerra-Alvarez; Rocío del Río; Francisco V. Fernández 001; Maria Belen Pérez-Verdú (Microelectron. J., 2009)

A memetic approach to the automatic design of high-performance analog integrated circuits. - Bo Liu 003; Francisco V. Fernández 001; Georges G. E. Gielen; Rafael Castro-López; Elisenda Roca (ACM Trans. Design Autom. Electr. Syst., 2009)

Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors. - Francisco V. Fernández 001; Juan Esteban-Muller; Elisenda Roca; Rafael Castro-López (IEEE Congress on Evolutionary Computation, 2010)

A 0.13 µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications. - Alonso Morgado; Rocío del Río Fernández; José M. de la Rosa 001; Rafael Castro-López; Maria Belen Pérez-Verdú (Microelectron. J., 2010)

Layout-aware Pareto fronts of electronic circuits. - Antonio Toro-Frías; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (ECCTD, 2011)

Implementation issues in the hierarchical composition of performance models of analog circuits. - Manuel Velasco-Jimenez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (DATE, 2014)

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. - Reinier Gonzalez-Echevarria; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Javier J. Sieiro; Neus Vidal; José María López-Villegas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Physical vs. surrogate models of passive RF devices. - Fábio Passos; Mouna Kotti; Reinier Gonzalez-Echevarria; M. Helena Fino; Mourad Fakhfakh; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (ISCAS, 2015)

Design space exploration using hierarchical composition of performance models. - Manuel Velasco-Jimenez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (ISCAS, 2015)

Accurate synthesis of integrated RF passive components using surrogate models. - Fábio Passos; Reinier Gonzalez-Echevarria; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (DATE, 2016)

Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. - Manuel Velasco-Jimenez; Rafael Castro-López; José M. de la Rosa 001 (ISCAS, 2016)

High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. - Manuel Velasco-Jimenez; Rafael Castro-López; José M. de la Rosa 001 (ISCAS, 2016)

SIDe-O: A toolbox for surrogate inductor design and optimization. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2016)

Frequency-dependent parameterized macromodeling of integrated inductors. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001; Y. Ye; Domenico Spina; Tom Dhaene (SMACD, 2016)

Reliability simulation for analog ICs: Goals, solutions, and challenges. - Antonio Toro-Frías; Pablo Martín-Lloret; Javier Martín-Martínez; Rafael Castro-López; Elisenda Roca; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (Integr., 2016)

An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (CEC, 2017)

A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs. - Pablo Martín-Lloret; Antonio Toro-Frías; Javier Martín-Martínez; Rafael Castro-López; Elisenda Roca; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (ISCAS, 2017)

TARS: A toolbox for statistical reliability modeling of CMOS devices. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Enrique Barajas; Xavier Aragonès; Diego Mateo (SMACD, 2017)

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. - Nuno C. Lourenço; Ricardo Martins 003; Ricardo Povoa; António Canelas; Nuno Horta; Fábio Passos; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

CASE: A reliability simulation tool for analog ICs. - Pablo Martín-Lloret; Antonio Toro-Frías; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría (SMACD, 2017)

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. - Ricardo Martins 003; Nuno C. Lourenço; Ricardo Povoa; António Canelas; Nuno Horta; Fábio Passos; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

Systematic design of a voltage controlled oscillator using a layout-aware approach. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001; Ricardo Martins 003; Nuno C. Lourenço; Ricardo Povoa; António Canelas; Nuno C. G. Horta (SMACD, 2017)

Including a stochastic model of aging in a reliability simulation flow. - Antonio Toro-Frías; Pablo Martín-Lloret; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría (SMACD, 2017)

Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (Appl. Soft Comput., 2017)

An inductor modeling and optimization toolbox for RF circuit design. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (Integr., 2017)

An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. - Reinier Gonzalez-Echevarria; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001; Javier J. Sieiro; José María López-Villegas; Neus Vidal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

CMOS Characterization and Compact Modelling for Circuit Reliability Simulation. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (IOLTS, 2018)

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. - Victor M. van Santen; Javier Diaz-Fortuny; Hussam Amrouch; Javier Martín-Martínez; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Jörg Henkel; Montserrat Nafría (IRPS, 2018)

Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology. - Enrique Barajas; Xavier Aragonès; Diego Mateo; Francesc Moll; Antonio Rubio 001; Javier Martín-Martínez; Rosana Rodríguez; Marc Porti; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (PATMOS, 2018)

A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Antonio Toro-Frías; Rafael Castro-López; Javier Martín-Martínez; Elisenda Roca; Rosana Rodríguez; Francisco V. Fernández 001; Montserrat Nafría (SMACD, 2018)

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. - Fábio Passos; Ricardo Martins 003; Nuno C. Lourenço; Elisenda Roca; Rafael Castro-López; Ricardo Povoa; António Canelas; Nuno Horta; Francisco V. Fernández 001 (SMACD, 2018)

Automated Massive RTN Characterization Using a Transistor Array Chip. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Antonio Toro-Frías; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. - Pablo Saraza-Canflanca; D. Malagon; Fábio Passos; A. Toro; Juan Núñez 002; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs. - Antonio Toro-Frías; Pablo Martín-Lloret; Javier Martín-Martínez; Rafael Castro-López; Elisenda Roca; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. - Fábio Passos; Ricardo Martins 003; Nuno Lourenço 003; Elisenda Roca; Ricardo Povoa; António Canelas; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (Integr., 2018)

A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca Moreno; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (DATE, 2019)

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator. - Antonio Toro-Frías; Pablo Saraza-Canflanca; Fábio Passos; Pablo Martín-Lloret; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (DATE, 2019)

A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices. - G. Pedreira; Javier Martín-Martínez; Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Montserrat Nafría (IRPS, 2019)

An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. - Pablo Martín-Lloret; Juan Núñez 002; Elisenda Roca; Rafael Castro-López; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

Experimental Characterization of Time-Dependent Variability in Ring Oscillators. - Juan Núñez 002; Elisenda Roca; Rafael Castro-López; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (SMACD, 2019)

TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Xavier Aragonès; Enrique Barajas; Diego Mateo; Francisco V. Fernández 001; Montserrat Nafría (IEEE J. Solid State Circuits, 2019)

A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits. - Fábio Passos; Reinier Gonzalez-Echevarria; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (Soft Comput., 2019)

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. - Ricardo Martins 003; Nuno Lourenço 003; Fábio Passos; Ricardo Povoa; António Canelas; Elisenda Roca; Rafael Castro-López; Javier J. Sieiro; Francisco V. Fernández 001; Nuno Horta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Improving the reliability of SRAM-based PUFs in the presence of aging. - Pablo Saraza-Canflanca; Héctor Carrasco-Lopez; Piedad Brox; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (DTIS, 2020)

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. - Fábio Passos; Elisenda Roca; Ricardo Martins 003; Nuno Lourenço 003; Saiyd Ahyoune; Javier J. Sieiro; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (IEEE Access, 2020)

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (Integr., 2020)

Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications. - Fábio Passos; Miguel Chanca; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. - Fábio Passos; Elisenda Roca; Javier J. Sieiro; Rafaella Fiorelli; Rafael Castro-López; José María López-Villegas; Francisco V. Fernández 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Francisco V. Fernández 001; Montserrat Nafría (IEEE Trans. Instrum. Meas., 2020)

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. - António Canelas; Fábio Passos; Nuno Lourenço 003; Ricardo Martins 003; Elisenda Roca; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (IEEE Access, 2021)

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies. - Pablo Saraza-Canflanca; Héctor Carrasco-Lopez; Andrés Santana-Andreo; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (IRPS, 2022)

A novel Physical Unclonable Function using RTN. - Eros Camacho-Ruiz; Rafael Castro-López; Elisenda Roca; Piedad Brox; Francisco V. Fernández 001 (ISCAS, 2022)

High-level design of a novel PUF based on RTN. - Eros Camacho-Ruiz; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2022)

On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF. - Eros Camacho-Ruiz; Andrés Santana-Andreo; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2022)

Machine Learning Approaches for Transformer Modeling. - Fábio Passos; Nuno C. Lourenço; Ricardo Martins 003; Elisenda Roca; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (SMACD, 2022)

Characterization and analysis of BTI and HCI effects in CMOS current mirrors. - Andrés Santana-Andreo; Pablo Martín-Lloret; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2022)

Impact of BTI and HCI on the reliability of a Majority Voter. - Andrés Santana-Andreo; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2022)

A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation. - Pablo Saraza-Canflanca; Javier Martín-Martínez; Elisenda Roca; Rafael Castro-López; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2022)

A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs. - Andrés Santana-Andreo; Pablo Saraza-Canflanca; Héctor Carrasco-Lopez; Piedad Brox; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (Integr., 2022)

On the Impact of the Biasing History on the Characterization of Random Telegraph Noise. - Pablo Saraza-Canflanca; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (IEEE Trans. Instrum. Meas., 2022)

Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability. - Javier Martín-Martínez; Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Montserrat Nafría (IRPS, 2023)

Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. - Victor M. van Santen; Jose M. Gata-Romero; Juan Núñez 002; Rafael Castro-López; Elisenda Roca; Hussam Amrouch (IRPS, 2023)

Design considerations for a CMOS 65-nm RTN-based PUF. - Eros Camacho-Ruiz; F. J. Rubio-Barbero; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2023)

Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices. - Francisco V. Fernández 001; Elisenda Roca; Pablo Saraza-Canflanca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López (SMACD, 2023)

Reliability evaluation of IC Ring Oscillator PUFs. - Jose M. Gata-Romero; Elisenda Roca; Juan Núñez 002; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2023)

A Test Module for Aging Characterization of Digital Circuits. - Jose M. Gata-Romero; Andrés Santana-Andreo; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2023)

A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF. - F. J. Rubio-Barbero; Eros Camacho-Ruiz; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2023)

A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array. - Andrés Santana-Andreo; Pablo Saraza-Canflanca; Héctor Carrasco-Lopez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2023)

Towards a Digital Twin of a Time-Dependent Variability Characterization Laboratory. - Jose M. Gata-Romero; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2024)

Harvesting RTN for True Random Number Generators and Physical Unclonable Functions. - F. J. Rubio-Barbero; F. de Los Santos-Prieto; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2024)

Streamlined design methodology for Cell-Based DCOs. - Andrés Santana-Andreo; Jose M. Gata-Romero; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2024)

Optimization-based bit selection technique to improve the reliability of PUFs. - F. de Los Santos-Prieto; F. J. Rubio-Barbero; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2024)

When Variability Meets Security. - Rafael Castro-López; Javier Diaz-Fortuny; Elisenda Roca; Francisco V. Fernández 001 (IRPS, 2025)

A Ring-Oscillator-based Odometer to Unveil the Actual IC Usage Time. - F. de Los Santos-Prieto; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; F. V. Fernandez (ISCAS, 2025)

Towards a Reliable PUF Using Organic Thin-Film Transistors. - F. de Los Santos-Prieto; Deborah Eric; Marc Porti; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Montserrat Nafría (SMACD, 2025)

A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs. - F. de Los Santos-Prieto; F. J. Rubio-Barbero; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)