A GPU-Based DVC to H.264/AVC Transcoder. - Alberto Corrales-García; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José M. Claver; José Luis Sánchez Garcia (HAIS (2), 2010)

Reducing complexity in H.264/AVC motion estimation by using a GPU. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José M. Claver; José L. Sánchez 002 (MMSP, 2011)

A Fast GPU-Based Motion Estimation Algorithm for HD 3D Video Coding. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (ISPA, 2012)

A Fast GPU-Based Motion Estimation Algorithm for H.264/AVC. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (MMM, 2012)

Optimizing H.264/AVC interprediction on a GPU-based framework. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José L. Sánchez 002; José M. Claver; Pedro Diaz (Concurr. Comput. Pract. Exp., 2012)

Low delay H.264/AVC bidirectional inter prediction on a GPU. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; José L. Sánchez 002; José M. Claver; Rik Van de Walle (ICIP, 2013)

Fast transrating for high efficiency video coding based on machine learning. - Luong Pham Van; Jan De Cock; Glenn Van Wallendael; Sebastiaan Van Leuven; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Peter Lambert; Rik Van de Walle (ICIP, 2013)

3D high definition video coding on a GPU-based heterogeneous system. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; Gerardo Fernández-Escribano; Bart Pieters; José L. Sánchez 002; José M. Claver; Rik Van de Walle (Comput. Electr. Eng., 2013)

Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Jan De Cock; Gerardo Fernández-Escribano; Bart Pieters; José L. Sánchez 002; José Manuel Claver; Rik Van de Walle (EURASIP J. Adv. Signal Process., 2013)

H.264/AVC inter prediction on accelerator-based multi-core systems. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Luis Sánchez Garcia; José Manuel Claver (Multim. Tools Appl., 2013)

H.264/AVC inter prediction for heterogeneous computing systems. - Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; José Manuel Claver; José L. Sánchez 002 (J. Supercomput., 2013)

Parallel performance and energy efficiency of modern video encoders on multithreaded architectures. - Rafael Rodríguez-Sánchez 001; Francisco D. Igual; José Luis Martínez 001; Rafael Mayo 002; Enrique S. Quintana-Ortí (EUSIPCO, 2014)

An smpUMHexagonS-based motion estimation algorithm for heterogeneous architectures. - Álvaro García; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001 (ICIP, 2014)

Time and energy modeling of an INTRA-ONLY HEVC encoder. - Rafael Rodríguez-Sánchez 001; Maria Teresa Alonso; José Luis Martínez 001; Rafael Mayo 002; Enrique S. Quintana-Ortí (VCIP, 2015)

HEVC to VP9 transcoder. - Enrique de la Torre; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001 (VCIP, 2015)

Multi-Threaded Dense Linear Algebra Libraries for Low-Power Asymmetric Multicore Processors. - Sandra Catalán; José R. Herrero 001; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (CoRR, 2015)

Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors. - Sandra Catalán; Francisco D. Igual; Rafael Mayo 002; Luis Piñuel; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (CoRR, 2015)

Time and energy modeling of high-performance Level-3 BLAS on x86 architectures. - Pedro Alonso 002; Sandra Catalán; Francisco D. Igual; Rafael Mayo 002; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (Simul. Model. Pract. Theory, 2015)

Fast video transcoding from HEVC to VP9. - Enrique de la Torre; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001 (IEEE Trans. Consumer Electron., 2015)

Multimedia Communications Using a Fast and Flexible DVC to H.264/AVC/SVC Transcoder. - Alberto Corrales-García; Rafael Rodríguez-Sánchez 001; José Luis Martínez 001; Gerardo Fernández-Escribano; Francisco J. Quiles 001 (J. Signal Process. Syst., 2015)

Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM big.LITTLE Architectures in Dense Linear Algebra. - Luis Costero; Francisco D. Igual; Katzalin Olcoz; Sandra Catalán; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (IPDPS Workshops, 2016)

Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors. - Sandra Catalán; Francisco D. Igual; Rafael Mayo 002; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (Clust. Comput., 2016)

Tiles-and WPP-based HEVC Decoding on Asymmetric Multi-core Processors. - Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (BigMM, 2017)

Static Versus Dynamic Task Scheduling of the Lu Factorization on ARM big. LITTLE Architectures. - Sandra Catalán; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí; José R. Herrero 001 (IPDPS Workshops, 2017)

Reduction to Tridiagonal Form for Symmetric Eigenproblems on Asymmetric Multicore Processors. - Pedro Alonso 002; Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (PMAM@PPoPP, 2017)

Two-Sided Reduction to Compact Band Forms with Look-Ahead. - Rafael Rodríguez-Sánchez 001; Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Andrés E. Tomás (CoRR, 2017)

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors. - Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (J. Real Time Image Process., 2017)

Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations. - Luis Costero; Francisco D. Igual; Katzalin Olcoz; Sandra Catalán; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (Parallel Comput., 2017)

Time and energy modeling of a high-performance multi-threaded Cholesky factorization. - Sandra Catalán; Francisco D. Igual; Rafael Mayo 002; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (J. Supercomput., 2017)

Reduction to Band Form for the Singular Value Decomposition on Graphics Accelerators. - Andrés E. Tomás; Rafael Rodríguez-Sánchez 001; Sandra Catalán; Enrique S. Quintana-Ortí (PMAM@PPoPP, 2018)

Multi-threaded dense linear algebra libraries for low-power asymmetric multicore processors. - Sandra Catalán; José R. Herrero 001; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí; Chris Adeniyi-Jones (J. Comput. Sci., 2018)

Two-sided orthogonal reductions to condensed forms on asymmetric multicore processors. - Pedro Alonso 002; Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (Parallel Comput., 2018)

Energy balance between voltage-frequency scaling and resilience for linear algebra routines on low-power multicore architectures. - Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (Parallel Comput., 2018)

Static scheduling of the LU factorization with look-ahead on asymmetric multicore processors. - Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (Parallel Comput., 2018)

A Case for Malleable Thread-Level Linear Algebra Libraries: The LU Factorization With Partial Pivoting. - Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001; Robert A. van de Geijn (IEEE Access, 2019)

Look-ahead in the two-sided reduction to compact band forms for symmetric eigenvalue problems and the SVD. - Rafael Rodríguez-Sánchez 001; Sandra Catalán; José R. Herrero 001; Enrique S. Quintana-Ortí; Andrés E. Tomás (Numer. Algorithms, 2019)

Dynamic look-ahead in the reduction to band form for the singular value decomposition. - Andrés E. Tomás; Rafael Rodríguez-Sánchez 001; Sandra Catalán; Rocío Carratalá-Sáez; Enrique S. Quintana-Ortí (Parallel Comput., 2019)

Programming parallel dense matrix factorizations with look-ahead and OpenMP. - Sandra Catalán; Adrián Castelló 001; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (Clust. Comput., 2020)

Integration and exploitation of intra-routine malleability in BLIS. - Rafael Rodríguez-Sánchez 001; Francisco D. Igual; Enrique S. Quintana-Ortí (J. Supercomput., 2020)

Scalable Hybrid Loop- and Task-Parallel Matrix Inversion for Multicore Processors. - Sandra Catalán; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (IPDPS Workshops, 2021)

A New Generation of Task-Parallel Algorithms for Matrix Inversion in Many-Threaded CPUs. - Sandra Catalán; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; José R. Herrero 001; Enrique S. Quintana-Ortí (PMAM@PPoPP, 2021)

Low precision matrix multiplication for efficient deep learning in NVIDIA Carmel processors. - Pablo San Juan; Rafael Rodríguez-Sánchez 001; Francisco D. Igual; Pedro Alonso-Jordá; Enrique S. Quintana-Ortí (J. Supercomput., 2021)

NUMA-Aware Dense Matrix Factorizations and Inversion with Look-Ahead on Multicore Processors. - Sandra Catalán; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; José R. Herrero 001; Enrique S. Quintana-Ortí (SBAC-PAD, 2022)

QR Factorization Using Malleable BLAS on Multicore Processors. - Adrián Castelló 001; Sandra Catalán; Francisco D. Igual; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (ISC Workshops, 2022)

Fine-grain task-parallel algorithms for matrix factorizations and inversion on many-threaded CPUs. - Sandra Catalán; José R. Herrero 001; Francisco D. Igual; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (Concurr. Comput. Pract. Exp., 2023)

Co-Design of the Dense Linear AlgebravSoftware Stack for Multicore Processors. - Héctor Martínez 002; Sandra Catalán; Francisco D. Igual; José R. Herrero 001; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (CoRR, 2023)

Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures. - Sandra Catalán; Francisco D. Igual; José R. Herrero 001; Rafael Rodríguez-Sánchez 001; Enrique S. Quintana-Ortí (J. Parallel Distributed Comput., 2023)

Inference with Transformer Encoders on ARM and RISC-V Multicore Processors. - Héctor Martínez 002; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Sandra Catalán; Adrián Castelló 001; Enrique S. Quintana-Ortí (Euro-Par (2), 2024)

Performance Analysis of BERT on RISC-V Processors with SIMD Units. - Héctor Martínez 002; Sandra Catalán; Carlos García 001; Francisco D. Igual; Rafael Rodríguez-Sánchez 001; Adrián Castelló 001; Enrique S. Quintana-Ortí (ISC Workshops, 2024)

Experiences with nested parallelism in task-parallel applications using malleable BLAS on multicore processors. - Rafael Rodríguez-Sánchez 001; Adrián Castelló 001; Sandra Catalán; Francisco D. Igual; Enrique S. Quintana-Ortí (Int. J. High Perform. Comput. Appl., 2024)