Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers. - Leandro M. G. Rocha; Guilherme Paim; Rafael S. Ferreira; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder. - Leandro M. G. Rocha; Guilherme Paim; Gustavo M. Santana; Brunno A. Abreu; Rafael Ferreira 001; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2017)

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding. - Bianca Silveira; Brunno Abreu; Guilherme Paim; Mateus Grellert; Rafael S. Ferreira; Cláudio Machado Diniz; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Low power sum of absolute differences architecture using novel hybrid adder. - Rafael Ferreira 001; Bianca Silveira; Mateus Beck Fonseca; Cláudio Machado Diniz; Eduardo A. C. da Costa (LASCAS, 2017)

Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform. - Guilherme Paim; Leonardo Bandeira Soares; Rafael S. Ferreira; Eduardo Costa 001; Sergio Bampi (NEWCAS, 2017)

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors. - Bianca Silveira; Rafael S. Ferreira; Guilherme Paim; Cláudio Machado Diniz; Eduardo A. C. da Costa (NEWCAS, 2017)

A power-predictive environment for fast and power-aware ASIC-based FIR filter design. - Guilherme Paim; Rafael S. Ferreira; Leandro M. G. Rocha; Eduardo A. C. da Costa; Tiago Giacomelli Alves; Sergio Bampi (SBCCI, 2017)

Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators. - Rafael Ferreira 001; Mateus Leme; Marcel Moscarelli Corrêa; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (ICECS, 2019)

HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. - Rafael S. Ferreira; Guilherme Paim; Brunno A. Abreu; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2019)

VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis. - Rafael S. Ferreira; Lucas Santos; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (ICECS 2022, 2022)

The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. - Bianca Silveira; Guilherme Paim; Brunno Alves Abreu; Rafael dos Santos Ferreira; Cláudio Machado Diniz; Eduardo Antônio César da Costa; Sergio Bampi (Circuits Syst. Signal Process., 2022)

Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding. - Rafael S. Ferreira; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (SBCCI, 2023)

A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning. - Ramiro Viana; Fernando Sagrilo; Rafael S. Ferreira; Marta Loose; Marcelo Schiavon Porto; Guilherme Corrêa 001; Luciano Agostini (LASCAS, 2024)

A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees. - Ramiro Viana; Marta Loose; Rafael S. Ferreira; Marcelo Schiavon Porto; Guilherme Corrêa 001; Luciano Agostini (SBCCI, 2024)

Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors. - Rafael Ferreira 001; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (LASCAS, 2025)