Infrastructure for dynamic reconfigurable systems: choices and trade-offs. - Leandro Möller; Rafael Soares; Ewerson Carvalho; Ismael Grehs; Ney Calazans; Fernando Moraes 001 (SBCCI, 2006)

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. - Julian J. H. Pontes; Rafael Soares; Ewerson Carvalho; Fernando Moraes 001; Ney Calazans (ICCD, 2007)

A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. - Leandro Möller; Ismael Grehs; Ewerson Carvalho; Rafael Soares; Ney Calazans; Fernando Moraes 001 (ReCoSoC, 2007)

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. - Julian J. H. Pontes; Matheus T. Moreira; Rafael Soares; Ney Laert Vilar Calazans (ISVLSI, 2008)

Triple Rail Logic Robustness against DPA. - Victor Lomné; Thomas Ordas; Philippe Maurine; Lionel Torres; Michel Robert; Rafael Soares; Ney Calazans (ReConFig, 2008)

Evaluating the robustness of secure triple track logic through prototyping. - Rafael Soares; Ney Laert Vilar Calazans; Victor Lomné; Philippe Maurine; Lionel Torres; Michel Robert (SBCCI, 2008)

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. - Victor Lomné; Philippe Maurine; Lionel Torres; Michel Robert; Rafael Soares; Ney Calazans (DATE, 2009)

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. - Rafael Soares; Ney Laert Vilar Calazans; Victor Lomné; Amine Dehbaoui; Philippe Maurine; Lionel Torres (SBCCI, 2010)

Arquitetura GALS pipeline para criptografia robusta a ataques DPA e DEMA. - Rafael Iankowski Soares (2010)

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. - Rafael Iankowski Soares; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Philippe Maurine; Lionel Torres (IEEE Des. Test Comput., 2011)

Information security aspects of public software. - Henrique Soares; Raphael Machado; Bruno Salgado; Rafael Soares; Jarbas Lopes Cardoso Jr.; Luis Felipe Costa (MEDES, 2013)

Evolução de requisitos na metodologia ágil. - Fernanda M. R. Alencar; Thiago Cabral; Rafael Soares (ER@BR, 2013)

Gerenciamento de Requisitos em Scrum baseado em Test Driven Development. - Rafael Soares; Thiago Cabral; Fernanda M. R. Alencar (ER@BR, 2013)

Engenharia de Requisitos: Um Survey realizado no Porto Digital, Recife/Brasil. - Darlan Arruda; Rafael Soares; Dércio Vieira; Thiago Cabral; Maria Lencastre 001; Rafael Ferreira (CIbSE, 2014)

Towards a Framework to Perform DPA Attack on GALS Pipeline Architectures. - Luciano Loder; Adão Antônio de Souza Jr.; Marcelo Schiavon Fay; Rafael Soares (SBCCI, 2014)

Low voltage low power current reference circuit for passive RFID applications. - Dalton Martini Colombo; Rafael Soares; Fabricio Mattos (LASCAS, 2016)

Range segmentation to improve latency in parallel stochastic computing. - Rai Saraiva; Julio C. Ruzicki; Adão Antônio de Souza Jr.; Rafael Iankowski Soares (LASCAS, 2016)

An energy-based attack flow for temporal misalignment coutermeasures on cryptosystems. - Rodrigo Lellis; Rafael Iankowski Soares; Adão Antônio de Souza Jr. (ISCAS, 2017)

A Novel Sizing Method Aiming Security Against Differential Power Analysis. - Vitor G. Lima; Plinio Finkenauer; Vinícius V. Camargo; Felipe S. Marques 001; Leomar R. Junior; Rafael Iankowski Soares (ICECS, 2018)

Developing a Corporate Chatbot for a Customer Engagement Program: A Roadmap. - Maria Fernanda Castro; Patrícia C. A. R. Tedesco; Havana Alves; Jonysberg P. Quintino; Juliana Steffen; Frederico Oliveira; Rafael Soares; André L. M. Santos; Fabio Q. B. da Silva (ICIC (1), 2018)

Phase Detection and Analysis among Multiple Program Inputs. - Rafael Soares; Luis Antonioli; Emilio Francesquini; Rodolfo Azevedo (WSCAD, 2018)

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. - Vitor G. Lima; Guilherme Paim; Leandro M. G. Rocha; Leomar S. da Rosa Jr.; Felipe S. Marques 001; Eduardo A. C. da Costa; Vinícius V. Camargo; Rafael Soares; Sergio Bampi (ISCAS, 2019)

Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS. - Rodrigo N. Wuerdig; Vitor G. Lima; Filipe D. Baumgratz; Rafael Soares; Sergio Bampi (LASCAS, 2020)

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture. - Mateus Terribele Leme; Guilherme Paim; Leandro M. G. Rocha; Patrícia Ücker; Vitor G. Lima; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2020)

Integration of Security Standards in DevOps Pipelines: An Industry Case Study. - Fabiola Moyon; Rafael Soares; Maria Pinto-Albuquerque; Daniel Méndez 001; Kristian Beckers (PROFES, 2020)

Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks. - Plinio Finkenauer; Henrique Kessler; Rafael Iankowski Soares; Vinícius V. Camargo (ISCAS, 2021)

Echo State network based soft sensor for Monitoring and Fault Detection of Industrial Processes. - Tiago Lemos; Luiz Felipe Campos; Afrânio Melo; Nayher Clavijo; Rafael Soares; Maurício Câmara; Thiago Feital; Thiago K. Anzai; José Carlos Pinto (Comput. Chem. Eng., 2021)

Fast Chaotic Image Encryption with Simultaneous Permutation and Diffusion for IoT Applications. - João Inácio Moreira Bezerra; Gustavo Machado; Rafael Soares; Alexandre Molter; Vinícius V. Camargo (GLOBECOM, 2022)

An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators. - Patrícia U. L. da Costa; Morgana M. A. da Rosa; Guilherme Paim; Eduardo Antonio Cesar da Costa; Rafael Soares; Sergio Bampi (ICECS 2022, 2022)

Pruning-based Neural Network Reduction for Faster Profiling Side-Channel Attacks. - Rodrigo Lellis; Rafael Soares; Guilherme Perin (ICECS 2022, 2022)

Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (ICECS 2022, 2022)

Fault Tolerance Evaluation of Different Majority Voter Designs. - Ingrid F. V. Oliveira; Matheus F. Pontes; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Paulo F. Butzen; Rafael Iankowski Soares (ISCAS, 2022)

AxRSU: Approximate Radix-4 Squarer Unit. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Jorge Castro-Godínez; Eduardo A. C. da Costa; Rafael Iankowski Soares; Sergio Bampi (ISCAS, 2022)

Alfaba: A Tangible Solution to Support Brazilian Dyslexic Students in their Literacy Process. - Laura Quevedo Jurgina; Lui Gill Aquini; Rafael Iankowski Soares; Leomar Soares da Rosa Jr.; Marilton Sanchotene de Aguiar; Tiago Thompsen Primo (EDUCON, 2023)

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression. - Arthur Cardozo; Morgana M. A. da Rosa; Rafael Soares; Eduardo Costa 001; Sergio Bampi (ICECS, 2023)

An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies. - Patrícia U. L. da Costa; Morgana M. A. da Rosa; Rafael Soares; Eduardo A. C. da Costa; Sergio Bampi (ICECS, 2023)

New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies. - Rodrigo Lopes; Leonardo Antonietti; Morgana M. A. da Rosa; Eduardo Costa 001; Rafael Soares; Sergio Bampi (ICECS, 2023)

Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder. - Morgana M. A. da Rosa; Eduardo Costa 001; Rafael Soares; Sergio Bampi (ICECS, 2023)

An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units. - Morgana M. A. da Rosa; Patrícia U. L. da Costa; Guilherme Paim; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (LASCAS, 2023)

Exploring Security Threats by Hardware-Faults in Approximate Arithmetic Computing. - Morgana Macedo Azevedo da Rosa; Eduardo A. C. da Costa; Rafael Iankowski Soares; Sergio Bampi (NEWCAS, 2023)

Improving an Ultra Lightweight AES for IoT Applications. - Yuri Silva Vaz; Júlio C. B. de Mattos; Rafael Iankowski Soares (WF-IoT, 2023)

AxPPA: Approximate Parallel Prefix Adders. - Morgana Macedo Azevedo da Rosa; Guilherme Paim; Patrícia Ücker Leleu da Costa; Eduardo Antonio Cesar da Costa; Rafael Iankowski Soares; Sergio Bampi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. - Tiago R. Balen; Carlos J. González; Ingrid F. V. Oliveira; Leomar S. da Rosa Jr.; Rafael Iankowski Soares; Rafael B. Schvittz; Nemitala Added; Eduardo L. A. Macchione; Vitor A. P. Aguiar; Marcilei Aparecida Guazzelli; Nilberto H. Medina; Paulo F. Butzen (J. Electron. Test., 2023)

Neuroplasticity-Based Literacy Rescue: A Multisensory and Tangible Learning Methodology for Children at Risk. - Laura Quevedo Jurgina; Lui Gill Aquini; Marilton Sanchotene de Aguiar; Leomar Soares da Rosa; João Pedro Lopes; Tiago Duarte Mackedanz; Angela Ines Klein; Tiago Thompsen Primo; Rafael Iankowski Soares (EDUCON, 2024)

PrompTCC: Transactional Causally Consistent Reads Can Be Fast and Fresh. - Taras Lykhenko; Rafael Soares; Luís Rodrigues (PRDC, 2024)

Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection. - Eloisa Barros; Morgana Macedo Azevedo da Rosa; Rodrigo Lopes; Leonardo Antonietti; Eduardo A. C. da Costa; Rafael Soares (SBCCI, 2024)

AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units. - Lourenço Mulling; Morgana Macedo Azevedo da Rosa; Rafael Soares; Eduardo A. C. da Costa (SBCCI, 2024)

Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design. - Léo Ribeiro; Morgana Macedo Azevedo da Rosa; Rafael Soares; Eduardo A. C. da Costa (SBCCI, 2024)

Lightweight AES Algorithm for Internet of Things: An Energy Consumption Analysis. - Yuri Silva Vaz; Júlio C. B. de Mattos; Rafael Iankowski Soares (SBESC, 2024)

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration. - Morgana Macedo Azevedo da Rosa; Patrícia Ücker Leleu da Costa; Eduardo Antonio Cesar da Costa; Rafael Iankowski Soares; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AxRSU-2m: Higher-Order m-Bit Approximate Encoders for Radix-2m Squarer Units. - Morgana M. A. da Rosa; Guilherme Paim; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (Circuits Syst. Signal Process., 2024)

A novel single kernel parallel image encryption scheme based on a chaotic map. - João Inácio Moreira Bezerra; Alexandre Molter; Gustavo Machado; Rafael Iankowski Soares; Vinícius V. Camargo (J. Real Time Image Process., 2024)

Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design. - Morgana M. A. da Rosa; Eduardo A. C. da Costa; Rafael Soares; Sergio Bampi (Circuits Syst. Signal Process., 2024)

Low-Energy NTT and INTT Architectures for Image Encryption and Decryption. - Eloisa Barros; Leonardo Antonietti; Rodrigo Lopes; Morgana da Rosa; Eduardo A. C. da Costa; Rafael Soares (ISCAS, 2025)

Exploring Approximate Adders for Energy-Efficient Discrete Walsh-Hadamard Transform. - Leonardo Antonietti; Rodrigo Lopes; Morgana M. A. da Rosa; Eloisa Barros; Eduardo A. C. da Costa; Rafael Soares (LASCAS, 2025)

Energy-Efficient PRNG Based on a Discrete-Space Chaotic Map Using an AxRMU Multiplier. - João Inácio Moreira Bezerra; Morgana Macedo Azevedo da Rosa; Leonardo Antonietti; Vinícius V. Camargo; Alexandre Molter; Rafael Iankowski Soares (LASCAS, 2025)

Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking Systems Design. - Morgana da Rosa; Eduardo Antonio Cesar da Costa; Rafael Soares (LASCAS, 2025)

A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal. - Henrique Seidel; Morgana M. A. da Rosa; Rodrigo Lopes; Eduardo A. C. da Costa; Rafael Soares (LASCAS, 2025)

High Throughput-to-Area AES: The Role of Small S-Box in Lightweight Cryptographic Design. - Yuri Silva Vaz; Júlio C. B. de Mattos; Rafael Iankowski Soares (LASCAS, 2025)

FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders. - Morgana Macedo Azevedo da Rosa; Leonardo Antonietti; Rodrigo Lopes; Eloisa Barros; Eduardo Antonio Cesar da Costa; Rafael Soares (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Automatic Design-Time Detection of Anomalies in Migrating Monolithic Applications to Microservices. - Valentim Romão; Rafael Soares; Luís Rodrigues; Vasco Manquinho (CoRR, 2025)

FPGA implementation of low cost and low power chaotic encryption scheme based on a discrete-space chaotic map. - João Inácio Moreira Bezerra; Gustavo Machado; Rafael Iankowski Soares; Vinícius Valduga de Almeida Camargo; Alexandre Molter (Multim. Tools Appl., 2025)