Optimized joint NARX ANN - embedded processor design methodology. - Rafael Trapani Possignolo; Omar Hammami (ICECS, 2009)

A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration. - Rafael Trapani Possignolo; Cíntia B. Margi (TrustCom, 2012)

Quantum-assisted QD-CFS signatures. - Rafael Trapani Possignolo; Cíntia Borges Margi; Paulo S. L. M. Barreto (J. Comput. Syst. Sci., 2015)

Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. - Ilya Ganusov; Henri Fraisse; Aaron Ng; Rafael Trapani Possignolo; Sabya Das (FPL, 2016)

LiveSynth: Towards an interactive synthesis flow. - Rafael Trapani Possignolo; Jose Renau (Hot Chips Symposium, 2016)

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Haven Blake Skinner; Jose Renau (ICCD, 2016)

SRAM voltage stacking. - Elnaz Ebrahimi 001; Rafael Trapani Possignolo; Jose Renau (ISCAS, 2016)

Managing Mismatches in Voltage Stacking with CoreUnfolding. - Ehsan K. Ardestani; Rafael Trapani Possignolo; José Luis Briz; Jose Renau (ACM Trans. Archit. Code Optim., 2016)

Level shifter design for voltage stacking. - Elnaz Ebrahimi 001; Rafael Trapani Possignolo; Jose Renau (ISCAS, 2017)

Liam: an actor based programming model for HDLs. - Haven Blake Skinner; Rafael Trapani Possignolo; Jose Renau (MEMOCODE, 2017)

Automated Pipeline Transformations with Fluid Pipelines. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Haven Blake Skinner; Jose Renau (Advanced Logic Synthesis, 2018)

GPU NTC Process Variation Compensation With Voltage Stacking. - Rafael Trapani Possignolo; Elnaz Ebrahimi 001; Ehsan K. Ardestani; Alamelu Sankaranarayanan; José Luis Briz; Jose Renau (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Improving the Productivity of Hardware Design. - Rafael Trapani Possignolo (2018)

SMatch: Structural Matching for Fast Resynthesis in FPGAs. - Rafael Trapani Possignolo; Jose Renau (DAC, 2019)

EMI Architectural Model and Core Hopping. - Daphne I. Gorman; Rafael Trapani Possignolo; Jose Renau (MICRO, 2019)

LiveSim: A Fast Hot Reload Simulator for HDLs. - Haven Blake Skinner; Rafael Trapani Possignolo; Sheng-Hong Wang; Jose Renau (ISPASS, 2020)

LiveHD: A Productive Live Hardware Development Flow. - Sheng-Hong Wang; Rafael Trapani Possignolo; Haven Blake Skinner; Jose Renau (IEEE Micro, 2020)