Shaik Rafi Ahamed
Orcid: 0000-0003-1617-2299
According to our database1,
Shaik Rafi Ahamed
authored at least 65 papers
between 2006 and 2024.
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Bibliography
2024
IEEE Access, 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
IEEE Internet Things J., August, 2023
IEEE Embed. Syst. Lett., March, 2023
IEEE Trans. Instrum. Meas., 2023
2022
An Efficient Scheme for Acoustic Echo Canceller Implementation Using Offset Binary Coding.
IEEE Trans. Instrum. Meas., 2022
High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Signal Process. Image Commun., 2022
A 28-Gbps Radix-16, 512-Point FFT Processor-Based Continuous Streaming OFDM for WiGig.
Circuits Syst. Signal Process., 2022
Two Distributed Arithmetic Based High Throughput Architectures of Non-Pipelined LMS Adaptive Filters.
IEEE Access, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
SN Comput. Sci., February, 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
High-Throughput and Improved-Convergent Design of Pipelined Adaptive DFE for 5G Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Distributed Arithmetic based realization of the Least Mean Square Adaptive Decision Feedback Equalizer with Offset Binary Coding scheme.
Signal Process., 2021
Fractional-Harris hawks optimization-based generative adversarial network for osteosarcoma detection using Renyi entropy-hybrid fusion.
Int. J. Intell. Syst., 2021
A Low-Complexity Shifting-Based Conflict-Free Memory-Addressing Architecture for Higher-Radix FFT.
IEEE Access, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
High-Performance Hardware Design of Block LMS Adaptive Noise Canceller for In-Ear Headphones.
IEEE Consumer Electron. Mag., 2020
Scalable VLSI Architecture for Hadamard Transforms of HEVC/H.265 Video Coding Standard.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IET Comput. Digit. Tech., 2019
Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT.
Proceedings of the National Conference on Communications, 2019
2018
J. Signal Process. Syst., 2018
Separation of Sources From Single-Channel EEG Signals Using Independent Component Analysis.
IEEE Trans. Instrum. Meas., 2018
Low Power Motion Estimation Algorithm and Architecture of HEVC/H.265 for Consumer Applications.
IEEE Trans. Consumer Electron., 2018
Design procedure for multifinger MOSFET two-stage OTA with shallow trench isolation effect.
IET Circuits Devices Syst., 2018
Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter.
IET Circuits Devices Syst., 2018
Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver.
IET Circuits Devices Syst., 2018
Circuits Syst. Signal Process., 2018
Programmable Cellular Automata-Based Low-Power Architecture to S-Box : An Application to WBAN.
Circuits Syst. Signal Process., 2018
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Analysis and Implementation of Block Least Mean Square Adaptive Filter using Offset Binary Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Consumer Electron., 2017
An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
An Ultra-Low-Voltage Bulk-Driven Analog Voltage Buffer with Rail-to-Rail Input/Output Range.
Circuits Syst. Signal Process., 2017
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Low Power S-Box Architecture for AES Algorithm using Programmable Second Order Reversible Cellular Automata: An Application to WBAN.
J. Medical Syst., 2016
DA based approach for the implementation of block adaptive decision feedback equaliser.
IET Signal Process., 2016
An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer.
Circuits Syst. Signal Process., 2016
Motion artifact removal from single channel electroencephalogram signals using singular spectrum analysis.
Biomed. Signal Process. Control., 2016
Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
2015
Analysis and algebraic construction of S-Box for AES algorithm using irreducible polynomials.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015
2014
Energy-Efficient and High-Speed Robust System Design for Remote Cardiac Health Monitoring.
J. Low Power Electron., 2014
Proceedings of the 9th International Conference on Body Area Networks, 2014
2013
Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A block floating point treatment to finite precision realization of the adaptive decision feedback equalizer.
Signal Process., 2013
Energy-Efficient and High-Speed Robust Channel Identification Methodology to Solve Permutation Indeterminacy in ICA for Artifacts Removal from ECG in Remote Healthcare.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Coordinate rotation based low complexity architecture for 3D Single Channel Independent Component Analysis.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
Int. J. Meas. Technol. Instrum. Eng., 2012
A Non-Linearities Based Noise Canceler for Cardiac Signal Enhancement in Wireless Health Care Monitoring.
Proceedings of the 2012 IEEE Global Humanitarian Technology Conference, 2012
2011
Efficient sign based normalized adaptive filtering techniques for cancelation of artifacts in ECG signals: Application to wireless biotelemetry.
Signal Process., 2011
2009
An Efficient Noise Cancellation Technique to Remove Noise from the ECG Signal Using Normalized Signed Regressor LMS Algorithm.
Proceedings of the 2009 IEEE International Conference on Bioinformatics and Biomedicine, 2009
2008
An efficient finite precision realization of the block adaptive decision feedback equalizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
An Efficient Implementation of the Sign LMS Algorithm Using Block Floating Point Format.
EURASIP J. Adv. Signal Process., 2007
An Efficient Finite Precision Realization of the Adaptive Decision Feedback Equalizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
The block LMS algorithm and its FFT based fast implementation - new efficient realization using block floating point arithmetic.
Proceedings of the 14th European Signal Processing Conference, 2006
An Efficient Realization of the Decision Feedback Equalizer using Block Floating Point Arithmetic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006