Comparative analysis of robustness of spin transfer torque based look up tables under process variations. - Ragh Kuttappa; Houman Homayoun; Hassan Salmani; Hamid Mahmoodi (ISCAS, 2016)

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging. - Ragh Kuttappa; Houman Homayoun; Hassan Salmani; Hamid Mahmoodi (Microelectron. Reliab., 2016)

Reconfigurable threshold logic gates using optoelectronic capacitors. - Ragh Kuttappa; Lunal Khuon; Bahram Nabet; Baris Taskin (DATE, 2017)

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. - Ragh Kuttappa; Leo Filippini; Scott Lerner; Baris Taskin (ISCAS, 2017)

Low Frequency Rotary Traveling Wave Oscillators. - Ragh Kuttappa; Baris Taskin (ISCAS, 2018)

Low Swing - Low Frequency Rotary Traveling Wave Oscillators. - Ragh Kuttappa; Scott Lerner; Leo Filippini; Baris Taskin (ISCAS, 2019)

Robust Low Power Clock Synchronization for Multi-Die Systems. - Ragh Kuttappa; Baris Taskin; Scott Lerner; Vasil Pano; Ioannis Savidis (ISLPED, 2019)

3D NoCs with active interposer for multi-die systems. - Vasil Pano; Ragh Kuttappa; Baris Taskin (NOCS, 2019)

Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation. - Longfei Wang; Ragh Kuttappa; Baris Taskin; Selçuk Köse (SLIP, 2019)

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. - Ragh Kuttappa; Adarsha Balaji; Vasil Pano; Baris Taskin; Hamid Mahmoodi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

FOPAC: Flexible On-Chip Power and Clock. - Ragh Kuttappa; Selçuk Köse; Baris Taskin (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

SnackNoC: Processing in the Communication Layer. - Karthik Sangaiah; Michael Lui; Ragh Kuttappa; Baris Taskin; Mark Hempstead (HPCA, 2020)

Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. - Ragh Kuttappa; Steven Khoa; Leo Filippini; Vasil Pano; Baris Taskin (ISCAS, 2020)

FinFET - Based Low Swing Rotary Traveling Wave Oscillators. - Ragh Kuttappa; Baris Taskin (ISCAS, 2020)

Scalable Resonant Power Clock Generation for Adiabatic Logic Design. - Ragh Kuttappa; Leo Filippini; Nicholas Sica; Baris Taskin (ISVLSI, 2021)

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. - Ragh Kuttappa; Baris Taskin; Scott Lerner; Vasil Pano (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators. - Ragh Kuttappa; Baris Taskin (ISCAS, 2022)

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. - Ragh Kuttappa; Baris Taskin; Vinayak Honkote; Satish Yada; Jainaveen Sundaram; Dileep Kurian; Tanay Karnik; Anuradha Srinivasan (ISCAS, 2022)

Multiphase Digital Low-Dropout Regulators. - Ragh Kuttappa; Longfei Wang; Selçuk Köse; Baris Taskin (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design Automation for Charge Recovery Logic. - Yilmaz Ege Gonul; Leo Filippini; Junghoon Oh; Ragh Kuttappa; Scott Lerner; Mineo Kaneko; Baris Taskin (ISCAS, 2024)

High-Speed Phase-Based Computing. - Nicholas Sica; Ragh Kuttappa; Vinayak Honkote; Baris Taskin (ISCAS, 2024)

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. - Vinayak Honkote; Ragh Kuttappa; Jainaveen Sundaram; Satish Yada; Chinnusamy Kalimuthu; Juhi Patil; Richard Lee; Cristan Paulino; Paolo A. Aseron; Trang Nguyen; Amreesh Rao; Dileep Kurian; et al. (VLSI Technology and Circuits, 2024)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)