Designing and validating an MD5 Hash Algorithm using the UVM Verification Framework and Checkers. - Kavin Kumar K; Nandhini V. D; Kowsalya M; Ragu P. J; Raghapriya N. R; S. Maheswaran 001 (ICCCNT, 2023)

FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications. - Pavithara P; Raghapriya N. R; P. M. Dinesh; S. Gowtham; D. Viji; K. Kavin Kumar; Gokul Chandrasekaran (ICCCNT, 2024)