Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. - Raghava Katreepalli; Hemanth Chemanchula; Themistoklis Haniotakis; Yiorgos Tsiatouhas (ISVLSI, 2016)

High Speed Power Efficient Carry Select Adder Design. - Raghava Katreepalli; Themistoklis Haniotakis (ISVLSI, 2017)

Power efficient synchronous counter design. - Raghava Katreepalli; Themistoklis Haniotakis (Comput. Electr. Eng., 2019)