A VLSI architecture for hierarchical scene matching. - R. Venkatesan; Raghu Sastry; N. Ranganathan (ICPR (4), 1992)

SMAC: A Scene Matching Chip. - N. Ranganathan; Raghu Sastry; Raguveer Venkatesan; Joseph W. Yoder; David C. Keezer (ICCD, 1993)

A Systolic Array for Approximate String Matching. - Raghu Sastry; N. Ranganathan (ICCD, 1993)

VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. - Raghu Sastry; N. Ranganathan; Ramesh C. Jain (IPPS, 1993)

Hardware Algorithms for Polygon Matching. - Raghu Sastry; N. Ranganathan; Horst Bunke (VLSI Design, 1993)

VLSI architectures for polygon recognition. - Raghu Sastry; N. Ranganathan; Horst Bunke (IEEE Trans. Very Large Scale Integr. Syst., 1993)

VLSI Architectures for Pattern Matching. - N. Ranganathan; Raghu Sastry (Int. J. Pattern Recognit. Artif. Intell., 1994)

A VLSI Architecture for Computer the Tree-to-Tree Distance. - Raghu Sastry; N. Ranganathan (HPCA, 1995)

PMAC: A Polygon Matching Chip. - Raghu Sastry; N. Ranganathan (Int. J. Pattern Recognit. Artif. Intell., 1995)

VLSI Architectures for High-Speed Range Estimation. - Raghu Sastry; N. Ranganathan; Ramesh C. Jain (IEEE Trans. Pattern Anal. Mach. Intell., 1995)

CASM: A VLSI Chip for Approximate String Matching. - Raghu Sastry; N. Ranganathan; Klinton Remedios (IEEE Trans. Pattern Anal. Mach. Intell., 1995)

A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip. - Albert Mu; Jeff Larson; Raghu Sastry; Thomas Wicki; Winfried W. Wilcke (COMPCON, 1996)

SMAC: A VLSI Architecture for Scene Matching. - N. Ranganathan; Raghu Sastry; Raguveer Venkatesan (Real Time Imaging, 1998)

A VLSI Architecture for Approximate Tree Matching. - Raghu Sastry; N. Ranganathan (IEEE Trans. Computers, 1998)