REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (ISVLSI, 2022)

DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (DFT, 2023)

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (IOLTS, 2023)

TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (DDECS, 2024)

TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (EWDTS, 2024)

GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (IOLTS, 2025)