Design Migration Across Technology - Making It Work. - Soumitra De Sirkar; Raghuram S. Tupuri; C. Sudha Madhuri; G. Rajagopalan; Kalpesh D. Mehta; C. G. Madhukar; Giridhar Bajpe (VLSI Design, 1992)

A Novel Functional Test Generation Method for Processors Using Commercial ATPG. - Raghuram S. Tupuri; Jacob A. Abraham (ITC, 1997)

A Novel Hierarchical Test Generation Method for Processors. - Raghuram S. Tupuri; Jacob A. Abraham (VLSI Design, 1997)

Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. - Raghuram S. Tupuri; Arun Krishnamachary; Jacob A. Abraham (DAC, 1999)

Hierarchical Test Generation for Systems On a Chip. - Raghuram S. Tupuri; Jacob A. Abraham; Daniel G. Saab (VLSI Design, 2000)

Timing Verification and Delay Test Generation for Hierarchical Designs. - Arun Krishnamachary; Jacob A. Abraham; Raghuram S. Tupuri (VLSI Design, 2001)

A Comprehensive Fault Model for Deep Submicron Digital Circuits. - Jacob A. Abraham; Arun Krishnamachary; Raghuram S. Tupuri (DELTA, 2002)

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. - Vivekananda M. Vedula; Jacob A. Abraham; Jayanta Bhadra; Raghuram S. Tupuri (J. Electron. Test., 2003)

Delay Constrained Register Transfer Level Dynamic Power Estimation. - Sriram Sambamurthy; Jacob A. Abraham; Raghuram S. Tupuri (PATMOS, 2006)

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. - Sriram Sambamurthy; Jacob A. Abraham; Raghuram S. Tupuri (VLSI Design, 2008)