High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design. - Rahebeh Niaraki Asli; Saeideh Shirinzadeh (J. Electron. Test., 2013)

A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology. - Rahebeh Niaraki Asli; Shiva Taghipour (J. Electron. Test., 2017)

Aging comparative analysis of high-performance FinFET and CMOS flip-flops. - Shiva Taghipour; Rahebeh Niaraki Asli (Microelectron. Reliab., 2017)

Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops. - Shiva Taghipour; Rahebeh Niaraki Asli (J. Electron. Test., 2019)

A new 7T SRAM cell in sub-threshold region with a high performance and small area with bit interleaving capability. - Maryam Nobakht; Rahebeh Niaraki Asli (IET Circuits Devices Syst., 2019)

An efficient design of low-power and high-speed approximate compressor in FinFET technology. - Pegah Zakian; Rahebeh Niaraki Asli (Comput. Electr. Eng., 2020)