Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. - Simon Tam 001; Rahul Dilip Limaye; Utpal Nagarji Desai (IEEE J. Solid State Circuits, 2004)

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. - Simon Tam 001; Justin Leung; Rahul Dilip Limaye; Sam Choy; Sujal Vora; Mitsuhiro Adachi (ISSCC, 2006)

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang; Brian S. Cherkauer; Jason Stinson; John Benoit; Raj Varada; Justin Leung; Rahul Dilip Limaye; Sujal Vora (IEEE J. Solid State Circuits, 2007)

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Satoshi Suzuki; Brent R. Carlton; Hyung Seok Kim; et al. (ISSCC, 2012)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)