Defect-Aware Design Paradigm for Reconfigurable Architectures. - Rahul Jain 004; Anindita Mukherjee; Kolin Paul (ISVLSI, 2006)

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. - Rahul Jain 004; Preeti Ranjan Panda (ISCAS, 2007)

Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. - Rahul Jain 004; Preeti Ranjan Panda (VLSI Design, 2007)

User-adaptive layer and power allocation for video multicast over wireless. - Rahul Jain 004; Swades De (NCC, 2015)

Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (DATE, 2016)

A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (DATE, 2017)

Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (ACM Trans. Archit. Code Optim., 2017)