Benchmarking Explicit State Parallel Model Checkers. - Michael D. Jones; Eric Mercer; Tonglaga Bao; Rahul Kumar 004; Peter Lamborn (PDMC@CAV, 2003)

Load Balancing Parallel Explicit State Model Checking. - Rahul Kumar 004; Eric G. Mercer (PDMC, 2004)

Improving Translation of Live Sequence Charts to Temporal Logic. - Rahul Kumar 004; Eric G. Mercer; Annette Bunker (AVoCS, 2007)

Improving Live Sequence Chart to Automata Transformation for Verification. - Rahul Kumar 004; Eric G. Mercer (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2008)

Verifying Communication Protocols Using Live Sequence Chart Specifications. - Rahul Kumar 004; Eric G. Mercer (AVoCS, 2008)