Frequency estimation by linear prediction. - Leland B. Jackson; Donald W. Tufts; Frank K. Soong; Rahul M. Rao (ICASSP, 1978)

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. - Rahul M. Rao; Jeffrey L. Burns; Richard B. Brown (ESSCIRC, 2003)

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. - Rahul M. Rao; Frank Liu 001; Jeffrey L. Burns; Richard B. Brown (ICCAD, 2003)

Leakage and leakage sensitivity computation for combinational circuits. - Emrah Acar; Anirudh Devgan; Rahul M. Rao; Ying Liu; Haihua Su; Sani R. Nassif; Jeffrey L. Burns (ISLPED, 2003)

Efficient techniques for gate leakage estimation. - Rahul M. Rao; Jeffrey L. Burns; Anirudh Devgan; Richard B. Brown (ISLPED, 2003)

Approaches to run-time and standby mode leakage reduction in global buses. - Rahul M. Rao; Kanak Agarwal 001; Dennis Sylvester; Richard B. Brown; Kevin J. Nowka; Sani R. Nassif (ISLPED, 2004)

Analysis and Optimization of Enhanced MTCMOS Scheme. - Rahul M. Rao; Jeffrey L. Burns; Richard B. Brown (VLSI Design, 2004)

Power-aware global signaling strategies. - Rahul M. Rao; Kanak Agarwal 001; Dennis Sylvester; Himanshu Kaul; Richard B. Brown; Sani R. Nassif (ISCAS (1), 2005)

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. - Harmander Deogun; Rahul M. Rao; Dennis Sylvester; Richard B. Brown; Kevin J. Nowka (ISQED, 2005)

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. - Rahul M. Rao; Kanak Agarwal 001; Anirudh Devgan; Kevin J. Nowka; Dennis Sylvester; Richard B. Brown (ISQED, 2005)

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength. - Harmander Singh Deogun; Dennis Sylvester; Rahul M. Rao; Kevin J. Nowka (SoCC, 2005)

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. - Kanak Agarwal 001; Rahul M. Rao; Dennis Sylvester; Richard B. Brown (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. - Saibal Mukhopadhyay; Rahul M. Rao; Jae-Joon Kim; Ching-Te Chuang (ISCAS, 2008)

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. - Amlan Ghosh; Rahul M. Rao; Ching-Te Chuang; Richard B. Brown (ISQED, 2008)

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. - Rahul M. Rao; Keith A. Jenkins; Jae-Joon Kim (ISSCC, 2008)

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. - Amlan Ghosh; Rahul M. Rao; Jae-Joon Kim; Ching-Te Chuang; Richard B. Brown (VLSI Design, 2008)

A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. - Amlan Ghosh; Richard B. Brown; Rahul M. Rao; Ching-Te Chuang (ISCAS, 2009)

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. - Amlan Ghosh; Rahul M. Rao; Richard B. Brown (ISLPED, 2009)

A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. - Rahul M. Rao; Keith A. Jenkins; Jae-Joon Kim (IEEE J. Solid State Circuits, 2009)

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. - Aditya Bansal; Rahul M. Rao; Jae-Joon Kim; Sufi Zafar; James H. Stathis; Ching-Te Chuang (Microelectron. Reliab., 2009)

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. - Jae-Joon Kim; Rahul M. Rao; Keunwoo Kim (CICC, 2010)

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. - Harmander Singh; Rahul M. Rao; Kanak Agarwal 001; Dennis Sylvester; Richard B. Brown (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Variations: Sources and Characterization. - Aditya Bansal; Rahul M. Rao (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. - Saibal Mukhopadhyay; Rahul M. Rao; Jae-Joon Kim; Ching-Te Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. - Yuma Higuchi; Kenichi Shinkai; Masanori Hashimoto; Rahul M. Rao; Sani R. Nassif (ETS, 2013)

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. - Nagu R. Dhanwada; David J. Hathaway; Victor V. Zyuban; Peng Peng; Karl Moody; William W. Dungan; Arun Joseph; Rahul M. Rao; Christopher J. Gonzalez (ICCAD, 2013)

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. - Amlan Ghosh; Rahul M. Rao; Jae-Joon Kim; Ching-Te Chuang; Richard B. Brown (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Virtual logic netlist: Enabling efficient RTL analysis. - Spandana Rachamalla; Arun Joseph; Rahul M. Rao; Diwesh Pandey (ISQED, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

FVCAG: A framework for formal verification driven power modeling and verification. - Arun Joseph; Spandana Rachamalla; Rahul M. Rao; Anand Haridass; Pradeep Kumar Nalla (ISLPED, 2016)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. - Sumantra Sarkar; Ayan Biswas; Anindya Sundar Dhar; Rahul M. Rao (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A High Performance Gated Voltage Level Translator with Integrated Multiplexer. - Dharshak B. S.; Rahul M. Rao (VLSID, 2018)

Impact of Device Aging on Early Mode Failures in Pulsed Latches. - Ankur Shukla; Rahul M. Rao; James D. Warnock (VLSID, 2018)

IBM POWER9 circuit design and energy optimization for 14-nm technology. - Eric J. Fluhr; Rahul M. Rao; Howard Smith; Alper Buyuktosunoglu; Ramon Bertran Monfort (IBM J. Res. Dev., 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. - Shivani Bathla; Rahul M. Rao; Nitin Chandrachoodan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. - Rahul M. Rao; Christopher J. Gonzalez; Eric Fluhr; Abraham Mathews; Andrew Bianchi; Daniel Dreps; David Wolpert 001; Eric Lai; Gerald Strevig; Glen A. Wiedemeier; Philipp Salz; Ryan Kruse (ISSCC, 2022)

Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning. - Naiju Karim Abdul; George Antony; Rahul M. Rao; Suriya T. Skariah (MLCAD, 2022)

Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. - George Antony; Gireesh Kumar K. M; Naiju Karim Abdul; Rahul M. Rao (DATE, 2024)

37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability. - David Wolpert 001; Gerry Strevig; Christopher J. Berry; Leon J. Sigal; Bill Huott; Mark Cichanowski; Matthias Pflanz; Tobias Werner 001; Philipp Salz; Nick Jinq; Michael Romain; Iris Leefken; et al. (ISSCC, 2025)

2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator. - Gerald Strevig; Christopher J. Berry; Rahul M. Rao; Noam Jungmann; Michael A. Sperling; Michael J. Becht; Eduard Herkel; Matthias Pflanz; Patrick J. Meaney; Michael Romain; Mark Cichanowski; Amanda Venton; et al. (ISSCC, 2025)