Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. - Rahul Shrestha; Roy P. Paily (VDAT, 2012)

A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. - Rahul Shrestha; Roy P. Paily (ICACCI, 2013)

Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. - Rahul Shrestha; Roy P. Paily (VLSI Design, 2013)

Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. - Rahul Shrestha; Roy P. Paily (IET Commun., 2013)

Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. - Rahul Shrestha; Roy Paily (ISED, 2014)

High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. - Rahul Shrestha; Roy P. Paily (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Machine learning for the activation of contraflows during hurricane evacuation. - John W. Burris; Rahul Shrestha; Bibek Gautam; Bibidh Bista (GHTC, 2015)

VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. - Rahul Shrestha; Roy P. Paily (J. Low Power Electron., 2015)

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. - Sachin Kumawat; Rahul Shrestha; Nikunj Daga; Roy P. Paily (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. - Rahul Shrestha; Roy P. Paily (J. Signal Process. Syst., 2015)

VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation. - Mahesh S. Murty; Rahul Shrestha (ISVLSI, 2016)

Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives. - Rahul Shrestha; Vinay Swargam; Mahesh S. Murty (VDAT, 2016)

Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. - Rahul Shrestha; Utkarsh Rastogiy (VLSID, 2016)

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. - Rahul Shrestha; Roy Paily (Circuits Syst. Signal Process., 2016)

Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. - Vijaya Kumar Kanchetla; Rahul Shrestha; Roy Paily (IET Circuits Devices Syst., 2016)

A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector. - B. Dinesh Kumar 001; Sumit Pandey; Puneet Arora; Rahul Shrestha (ISED, 2017)

Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform. - Rahul Kurzekar; Hardik Arora; Rahul Shrestha (iNIS, 2017)

A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. - Naman Govil; Rahul Shrestha; Shubhajit Roy Chowdhury (VDAT, 2017)

Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization. - Sumanth Gudaparthi; Rahul Shrestha (VDAT, 2017)

High-speed and low-power VLSI-architecture for inexact speculative adder. - Rahul Shrestha (VLSI-DAT, 2017)

PGMA: An algorithmic approach for multi-objective hardware software partitioning. - Naman Govil; Rahul Shrestha; Shubhajit Roy Chowdhury (Microprocess. Microsystems, 2017)

Parameterized Posit Arithmetic Hardware Generator. - Rohit Chaurasiya; John L. Gustafson; Rahul Shrestha; Jonathan Neudorfer; Sangeeth Nambiar; Kaustav Niyogi; Farhad Merchant; Rainer Leupers (ICCD, 2018)

Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices. - Rahul Shrestha; Ashutosh Sharma (VDAT, 2018)

VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. - Rahul Shrestha; Ashutosh Sharma (VLSI-SoC, 2018)

Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. - Mahesh S. Murty; Rahul Shrestha (VLSID, 2018)

Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network. - Mahesh S. Murty; Rahul Shrestha (IET Circuits Devices Syst., 2018)

Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks. - Mahesh S. Murty; Rahul Shrestha (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio. - Rohit B. Chaurasiya; Rahul Shrestha (ISCAS, 2019)

High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. - Rahul Shrestha; Pooja Bansal; Srikant Srinivasan (VLSID, 2019)

Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder. - Rahul Shrestha; Abhijit Sahoo (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network. - Rahul Shrestha; Shubham Sanjay Telgote (ISCAS, 2020)

A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard. - Anuj Verma; Rahul Shrestha (ISCAS, 2020)

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. - Anuj Verma; Rahul Shrestha (VLSID, 2020)

Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (ISCAS, 2021)

Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture. - Anuj Verma; Rahul Shrestha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications. - Rahul Shrestha (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications. - Md. Najrul Islam; Rahul Shrestha; Shubhajit Roy Chowdhury (ISVLSI, 2022)

High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems. - Kumari Suravi; Rahul Shrestha (ISVLSI, 2022)

Selective register-file cache: an energy saving technique for embedded processor architecture. - Sumanth Gudaparthi; Rahul Shrestha (Des. Autom. Embed. Syst., 2022)

Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Consumer Electron., 2022)

Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network. - Rohit B. Chaurasiya; Rahul Shrestha (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks. - Md. Najrul Islam; Rahul Shrestha; Shubhajit Roy Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method. - Rahul Sharma; Rahul Shrestha; Satinder K. Sharma (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal. - Lalit Kumar; Rahul Shrestha (J. Signal Process. Syst., 2022)

Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. - Meghvern Pathak; Rahul Shrestha (VLSID, 2023)

Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes. - Anuj Verma; Rahul Shrestha (IEEE Trans. Veh. Technol., 2023)

Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network. - Rahul Sharma; Rahul Shrestha; Satinder K. Sharma (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks. - Dayan Adionel Guimarães; Elivander J. T. Pereira; Rahul Shrestha (IEEE Trans. Veh. Technol., 2023)

Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator. - Md. Najrul Islam; Rahul Shrestha; Shubhajit Roy Chowdhury (VLSID, 2024)

A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network. - Shakti Singh; Rahul Shrestha (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion-Based Cooperative Cognitive-Radio Network. - Shakti Singh; Rahul Shrestha (IEEE Trans. Consumer Electron., 2024)

VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing. - Elivander J. T. Pereira; Dayan Adionel Guimarães; Rahul Shrestha (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications. - Md. Najrul Islam; Rahul Shrestha; Shubhajit Roy Chowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications. - Anuj Verma; Rahul Shrestha (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber. - Alip Majumdar; Rahul Shrestha (VLSID, 2025)