Test Generation for Digital Systems Based on Alternative Graphs. - Raimund Ubar (EDCC, 1994)

Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. - Raimund Ubar; Marina Brik (EDCC, 1996)

Test Synthesis with Alternative Graphs. - Raimund Ubar (IEEE Des. Test Comput., 1996)

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. - Alfredo Benso; Paolo Prinetto; Maurizio Rebaudengo; Matteo Sonza Reorda; Raimund Ubar (ED&TC, 1997)

Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. - Alfredo Benso; Paolo Prinetto; Maurizio Rebaudengo; Matteo Sonza Reorda; Jaan Raik; Raimund Ubar (DFT, 1997)

Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. - Raimund Ubar; Dominique Borrione (SBCCI, 1998)

Sequential Circuit Test Generation Using Decision Diagram Models. - Jaan Raik; Raimund Ubar (DATE, 1999)

Cycle-based Simulation with Decision Diagrams. - Raimund Ubar; Jaan Raik; Adam Morawiec (DATE, 1999)

High-level path activation technique to speed up sequential circuit test generation. - Jaan Raik; Raimund Ubar (ETW, 1999)

Design Error Diagnosis in Digital Circuits without Error Model. - Raimund Ubar; Dominique Borrione (VLSI, 1999)

Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. - Adam Morawiec; Raimund Ubar; Jaan Raik (DATE, 2000)

Test Cost Minimization for Hybrid Bist. - Gert Jervan; Zebo Peng; Raimund Ubar (DFT, 2000)

Hierarchical defect-oriented fault simulation for digital circuits. - Mykola Blyzniuk; T. Cibáková; Elena Gramatová; Wieslaw Kuzmicz; M. Lobur; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ETW, 2000)

Back-tracing and event-driven techniques in high-level simulation with decision diagrams. - Raimund Ubar; Jaan Raik; Adam Morawiec (ISCAS, 2000)

Efficient Hierarchical Approach to Test Generation for Digital Systems. - Raimund Ubar; Jaan Raik (ISQED, 2000)

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. - Jaan Raik; Raimund Ubar (J. Electron. Test., 2000)

Timing simulation of digital circuits with binary decision diagrams. - Raimund Ubar; Artur Jutman; Zebo Peng (DATE, 2001)

Fast Test Cost Calculation for Hybrid BIST in Digital Systems. - Elmet Orasson; Rein Raidma; Raimund Ubar; Gert Jervan; Zebo Peng (DSD, 2001)

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. - Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ISQED, 2001)

Design Error Diagnosis in Scan-Path Designs. - Raimund Ubar (LATW, 2001)

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. - Mykola Blyzniuk; Irena Kazymyra; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2001)

Internet-Based Collaborative Test Generation with MOSCITO. - André Schneider; Karl-Heinz Diener; Eero Ivask; Jaan Raik; Raimund Ubar; P. Miklos; T. Cibáková; Elena Gramatová (DATE, 2002)

Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. - Raimund Ubar; Jaan Raik; Eero Ivask; Marina Brik (DELTA, 2002)

Integrated Design and Test Generation Under Internet Based Environment MOSCITO. - André Schneider; Karl-Heinz Diener; Eero Ivask; Raimund Ubar; Elena Gramatová; Thomas Hollstein; Wieslaw Kuzmicz; Zebo Peng (DSD, 2002)

Practical works for on-line teaching design and test of digital circuits. - Artur Jutman; Raimund Ubar; Vladimir Hahanov; O. Skvortsova (ICECS, 2002)

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. - Jaan Raik; Artur Jutman; Raimund Ubar (ICECS, 2002)

A Hybrid BIST Architecture and Its Optimization for SoC Testing. - Gert Jervan; Zebo Peng; Raimund Ubar; Helena Kruus (ISQED, 2002)

Testability Calculation for Digital Circuits with Decision Diagrams. - Raimund Ubar (LATW, 2002)

Hierarchical test generation for combinational circuits with real defects coverage. - T. Cibáková; Mária Fischerová; Elena Gramatová; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2002)

Testing Strategies for Networks on Chip. - Raimund Ubar; Jaan Raik (Networks on Chip, 2003)

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. - Gert Jervan; Petru Eles; Zebo Peng; Raimund Ubar; Maksim Jenihhin (DFT, 2003)

Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. - Vladimir Hahanov; Raimund Ubar; Stanley Hyduke (DSD, 2003)

Conference Reports. - Vladimir Hahanov; Raimund Ubar (IEEE Des. Test Comput., 2003)

Design Error Diagnosis with Re-Synthesis in Combinational Circuits. - Raimund Ubar (J. Electron. Test., 2003)

Asynchronous e-learning resources for hardware design issues. - Artur Jutman; Alexander Sudnitson; Raimund Ubar; Heinz-Dietrich Wuttke (CompSysTech, 2004)

Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. - Raimund Ubar; Maksim Jenihhin (DELTA, 2004)

Web-Based Environment for Digital Electronics Test Tools. - Eero Ivask; Jaan Raik; Raimund Ubar; André Schneider (Virtual Enterprises and Collaborative Networks, 2004)

Conference Reports. - Vladimir Hahanov; Raimund Ubar; Subhasish Mitra (IEEE Des. Test Comput., 2004)

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. - Artur Jutman; Jaan Raik; Raimund Ubar; V. Vislogubov (DSD, 2005)

Improved Fault Emulation for Synchronous Sequential Circuits. - Jaan Raik; Peeter Ellervee; Valentin Tihhomirov; Raimund Ubar (DSD, 2005)

Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. - Joachim Sudbrock; Jaan Raik; Raimund Ubar; Wieslaw Kuzmicz; Witold A. Pleskacz (DSD, 2005)

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. - Jaan Raik; Raimund Ubar; Sergei Devadze; Artur Jutman (EDCC, 2005)

DOT: new deterministic defect-oriented ATPG tool. - Jaan Raik; Raimund Ubar; Joachim Sudbrock; Wieslaw Kuzmicz; Witold A. Pleskacz (ETS, 2005)

Energy minimization for hybrid BIST in a system-on-chip test environment. - Raimund Ubar; Tatjana Shchenova; Gert Jervan; Zebo Peng (ETS, 2005)

A New Testability Calculation Method to Guide RTL Test Generation. - Jaan Raik; Tanel Nõmmeots; Raimund Ubar (J. Electron. Test., 2005)

An External Test Approach for Network-on-a-Chip Switches. - Jaan Raik; Vineeth Govind; Raimund Ubar (ATS, 2006)

Off-Line Testing of Delay Faults in NoC Interconnects. - Tomas Bengtsson; Artur Jutman; Shashi Kumar; Raimund Ubar; Zebo Peng (DSD, 2006)

High-Level Decision Diagram based Fault Models for Targeting FSMs. - Jaan Raik; Raimund Ubar; Taavi Viilukas (DSD, 2006)

Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. - Sergei Devadze; Jaan Raik; Artur Jutman; Raimund Ubar (LATW, 2006)

DefSim: CMOS Defects on Chip for Research and Education. - Witold A. Pleskacz; Tomasz Borejko; Andrzej Walkanis; Viera Stopjaková; Artur Jutman; Raimund Ubar (LATW, 2006)

Test Time Minimization for Hybrid BIST of Core-Based Systems. - Gert Jervan; Petru Eles; Zebo Peng; Raimund Ubar; Maksim Jenihhin (J. Comput. Sci. Technol., 2006)

Layout to Logic Defect Analysis for Hierarchical Test Generation. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Witold A. Pleskacz; Michal Rakowski (DDECS, 2007)

Hierarchical Identification of Untestable Faults in Sequential Circuits. - Jaan Raik; Raimund Ubar; Anna Krivenko; Margus Kruus (DSD, 2007)

Fault Diagnosis in Integrated Circuits with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik; Teet Evartson; Harri Lensen (DSD, 2007)

Test Configurations for Diagnosing Faulty Links in NoC Switches. - Jaan Raik; Raimund Ubar; Vineeth Govind (ETS, 2007)

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ETS, 2007)

Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. - Gert Jervan; Helena Kruus; Elmet Orasson; Raimund Ubar (SIES, 2007)

FPGA-based fault emulation of synchronous sequential circuits. - Peeter Ellervee; Jaan Raik; Kalle Tammemäe; Raimund Ubar (IET Comput. Digit. Tech., 2007)

Learning Digital Test and Diagnostics via Internet. - Raimund Ubar; Artur Jutman; Margus Kruus; Elmet Orasson; Sergei Devadze; Heinz-Dietrich Wuttke (Int. J. Online Eng., 2007)

Parallel fault backtracing for calculation of fault coverage. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ASP-DAC, 2008)

Untestable Fault Identification in Sequential Circuits Using Model-Checking. - Jaan Raik; Hideo Fujiwara; Raimund Ubar; Anna Krivenko (ATS, 2008)

Web-Based Framework for Parallel Distributed Test. - Eero Ivask; Jaan Raik; Raimund Ubar (DDECS, 2008)

Calculation of LFSR Seed and Polynomial Pair for BIST Applications. - Artur Jutman; Anton Tsertov; Raimund Ubar (DDECS, 2008)

Code Coverage Analysis using High-Level Decision Diagrams. - Jaan Raik; Uljana Reinsalu; Raimund Ubar; Maksim Jenihhin; Peeter Ellervee (DDECS, 2008)

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. - Raimund Ubar; Sergei Devadze; Maksim Jenihhin; Jaan Raik; Gert Jervan; Peeter Ellervee (DELTA, 2008)

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. - Witold A. Pleskacz; Maksim Jenihhin; Jaan Raik; Michal Rakowski; Raimund Ubar; Wieslaw Kuzmicz (DSD, 2008)

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (ETS, 2008)

Reseeding using compaction of pre-generated LFSR sub-sequences. - Artur Jutman; Igor Aleksejev; Jaan Raik; Raimund Ubar (ICECS, 2008)

Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. - Eero Ivask; Jaan Raik; Raimund Ubar (IDC, 2008)

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. - Tomas Bengtsson; Shashi Kumar; Raimund Ubar; Artur Jutman; Zebo Peng (IET Comput. Digit. Tech., 2008)

Mixed hierarchical-functional fault models for targeting sequential cores. - Jaan Raik; Raimund Ubar; Taavi Viilukas; Maksim Jenihhin (J. Syst. Archit., 2008)

Hybrid BIST optimization using reseeding and test set compaction. - Gert Jervan; Elmet Orasson; Helena Kruus; Raimund Ubar (Microprocess. Microsystems, 2008)

Embedded fault diagnosis in digital systems with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik (Microprocess. Microsystems, 2008)

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. - Raimund Ubar; Sergei Kostin; Jaan Raik (DSD, 2009)

Structurally synthesized multiple input BDDs for simulation of digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ICECS, 2009)

Fast extended test access via JTAG and FPGAs. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (ITC, 2009)

Turning JTAG inside out for fast extended test access. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (LATW, 2009)

High-Level Decision Diagrams based coverage metrics for verification and test. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Uljana Reinsalu; Raimund Ubar (LATW, 2009)

Investigations of the diagnosibility of digital networks with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik (LATW, 2009)

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. - Raimund Ubar; Artur Jutman; Jaan Raik; Sergei Kostin; Heinz-Dietrich Wuttke (MSE, 2009)

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (J. Electron. Test., 2009)

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. - Jaan Raik; Vineeth Govind; Raimund Ubar (IET Comput. Digit. Tech., 2009)

Parallel X-fault simulation with critical path tracing technique. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DATE, 2010)

Constraint-based test pattern generation at the Register-Transfer Level. - Taavi Viilukas; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Anna Krivenko (DDECS, 2010)

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DELTA, 2010)

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. - Dmitri Mironov; Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DSD, 2010)

An approach for PSL assertion coverage analysis with high-level decision diagrams. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Tatjana Shchenova (EWDTS, 2010)

Collaborative Distributed Fault Simulation for Digital Electronic Circuits. - Eero Ivask; Sergei Devadze; Raimund Ubar (IDC, 2010)

Collaborative Distributed Computing in the Field of Digital Electronics Testing. - Eero Ivask; Sergei Devadze; Raimund Ubar (BASYS, 2010)

Fault collapsing with linear complexity in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISCAS, 2010)

Remote and Virtual Laboratories in Problem-Based Learning Scenarios. - Heinz-Dietrich Wuttke; Raimund Ubar; Karsten Henke (ISM, 2010)

Structural fault collapsing by superposition of BDDs for test generation in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISQED, 2010)

Mutation analysis with high-level decision diagrams. - Hanno Hantson; Jaan Raik; Maksim Jenihhin; Anton Chepurov; Raimund Ubar; Giuseppe Di Guglielmo; Franco Fummi (LATW, 2010)

Evolutionary Approach to Test Generation for Functional BIST - Yuriy A. Skobtsov; D. E. Ivanov; V. Y. Skobtsov; Raimund Ubar; Jaan Raik (CoRR, 2010)

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (Asian Test Symposium, 2011)

Probabilistic equivalence checking based on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (DDECS, 2011)

Defect-oriented module-level fault diagnosis in digital circuits. - Sergei Kostin; Raimund Ubar; Jaan Raik (DDECS, 2011)

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. - Uljana Reinsalu; Jaan Raik; Raimund Ubar; Peeter Ellervee (DFT, 2011)

SoC and Board Modeling for Processor-Centric Board Testing. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (DSD, 2011)

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. - Jaan Raik; Anna Rannaste; Maksim Jenihhin; Taavi Viilukas; Raimund Ubar; Hideo Fujiwara (ETS, 2011)

Automated test bench generation for high-level synthesis flow ABELITE. - Taavi Viilukas; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Samary Baranov (EWDTS, 2011)

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (HLDVT, 2011)

Mutation analysis for SystemC designs at TLM. - Valerio Guarnieri; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2011)

Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. - Eero Ivask; Sergei Devadze; Raimund Ubar (Scalable Comput. Pract. Exp., 2011)

Multiple stuck-at-fault detection theorem. - Raimund Ubar; Sergei Kostin; Jaan Raik (DDECS, 2012)

How to Prove that a Circuit is Fault-Free? - Raimund Ubar; Sergei Kostin; Jaan Raik (DSD, 2012)

Combining dynamic slicing and mutation operators for ESL correction. - Urmas Repinski; Hanno Hantson; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Giuseppe Di Guglielmo; Graziano Pravadelli; Franco Fummi (ETS, 2012)

Automated correction of design errors by edge redirection on High-Level Decision Diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (ISQED, 2012)

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. - Hanno Hantson; Urmas Repinski; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2012)

About robustness of test patterns regarding multiple faults. - Raimund Ubar; Sergei Kostin; Jaan Raik (LATW, 2012)

Functional Built-In Self-Test for processor cores in SoC. - Raimund Ubar; Viljar Indus; Oliver Kalmend; Teet Evartson; Elmet Orasson (NORCHIP, 2012)

On the Reuse of TLM Mutation Analysis at RTL. - Valerio Guarnieri; Giuseppe Di Guglielmo; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (J. Electron. Test., 2012)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)

Identifying NBTI-Critical Paths in Nanoscale Logic. - Raimund Ubar; Fabian Vargas 001; Maksim Jenihhin; Jaan Raik; Sergei Kostin; Letícia Maria Bolzani Poehls (DSD, 2013)

Synthesis of multiple fault oriented test groups from single fault test sets. - Raimund Ubar; Sergei Kostin; Jaan Raik (DTIS, 2013)

Assessment of diagnostic test for automated bug localization. - Valentin Tihhomirov; Anton Tsepurov; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATW, 2013)

Diagnostic modeling of digital systems with low- and high-level decision diagrams. - Raimund Ubar (LATW, 2013)

At-speed self-testing of high-performance pipe-lined processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (NORCHIP, 2013)

Automated design error debug using high-level decision diagrams and mutation operators. - Jaan Raik; Urmas Repinski; Anton Chepurov; Hanno Hantson; Raimund Ubar; Maksim Jenihhin (Microprocess. Microsystems, 2013)

Accurate Dialysis Dose Evaluation and Extrapolation Algorithms During Online Optical Dialysis Monitoring. - Ivo Fridolin; Deniss Karai; Sergei Kostin; Raimund Ubar (IEEE Trans. Biomed. Eng., 2013)

Lower bounds of the size of Shared Structurally Synthesized BDDs. - Raimund Ubar; Dmitri Mironov (DDECS, 2014)

Critical Path Tracing Based Simulation of Transition Delay Faults. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (DSD, 2014)

Logic simulation and fault collapsing with shared structurally synthesized bdds. - Dmitri Mironov; Raimund Ubar; Jaan Raik (ETS, 2014)

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. - Marco Gaudesi; Maksim Jenihhin; Jaan Raik; Ernesto Sánchez 001; Giovanni Squillero; Valentin Tihhomirov; Raimund Ubar (EvoApplications, 2014)

Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov; Helena Kruus (EWME, 2014)

Advanced technical education in the age of cyber physical systems. - Heinrich Theodor Vierhaus; Mario Schölzel; Jaan Raik; Raimund Ubar (EWME, 2014)

Modeling sequential circuits with shared structurally synthesized BDDs. - Raimund Ubar; Mihhail Marenkov; Dmitri Mironov; Vladimir Viies (IDT, 2014)

Hierarchical identification of NBTI-critical gates in nanoscale logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Fabian Vargas 001; Letícia Maria Bolzani Poehls; Thiago Santos Copetti (LATW, 2014)

Software-based self-test generation for microprocessors with high-level decision diagrams. - Raimund Ubar; Anton Tsertov; Artjom Jasnetski; Marina Brik (LATW, 2014)

Automated Design Error Localization in RTL Designs. - Maksim Jenihhin; Anton Tsepurov; Valentin Tihhomirov; Jaan Raik; Hanno Hantson; Raimund Ubar; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (IEEE Des. Test, 2014)

Fault simulation with parallel exact critical path tracing in multiple core environment. - Maksim Gorev; Raimund Ubar; Sergei Devadze (DATE, 2015)

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. - Artjom Jasnetski; Jaan Raik; Anton Tsertov; Raimund Ubar (DDECS, 2015)

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Thiago Copetti; Fabian Vargas 001; Letícia Maria Bolzani Pöhls (DDECS, 2015)

Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Galina Josifovska; Stephen Adeboye Oyeniran (DSD, 2015)

Multiple fault testing in systems-on-chip with high-level decision diagrams. - Raimund Ubar; Stephen Adeboye Oyeniran; Mario Schölzel; Heinrich Theodor Vierhaus (IDT, 2015)

Combinational fault simulation in sequential circuits. - Raimund Ubar; Jaak Kousaar; Maksim Gorev; Sergei Devadze (ISCAS, 2015)

Complex delay fault reasoning with sequential 7-valued algebra. - Jaak Kousaar; Raimund Ubar; Igor Aleksejev (LATS, 2015)

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. - Raimund Ubar; Lembit Jurimagi; Jaan Raik (NORCAS, 2015)

Scalable algorithm for structural fault collapsing in digital circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Jaan Raik (VLSI-SoC, 2015)

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. - Raimund Ubar; Lembit Jürimägi; Elmet Orasson; Jaan Raik (VLSI-SoC (Selected Papers), 2015)

Functional self-test of high-performance pipe-lined signal processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (Microprocess. Microsystems, 2015)

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (Microprocess. Microsystems, 2015)

Multiple control fault testing in digital systems with high-level decision diagrams. - Raimund Ubar; Stephen Adeboye Oyeniran (AQTR, 2016)

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. - Francesco Pellerey; Maksim Jenihhin; Giovanni Squillero; Jaan Raik; Matteo Sonza Reorda; Valentin Tihhomirov; Raimund Ubar (ATS, 2016)

High-level modeling and testing of multiple control faults in digital systems. - Artjom Jasnetski; Stephen Adeboye Oyeniran; Anton Tsertov; Mario Schölzel; Raimund Ubar (DDECS, 2016)

A tool set for teaching design-for-testability of digital circuits. - Sergei Kostin; Elmet Orasson; Raimund Ubar (EWME, 2016)

Gate-level modelling of NBTI-induced delays under process variations. - Thiago Copetti; Guilherme Medeiros Machado; Leticia Bolzani Poehls; Fabian Vargas 001; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATS, 2016)

On automatic software-based self-test program generation based on high-level decision diagrams. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov (LATS, 2016)

A novel random approach to diagnostic test generation. - Emmanuel Ovie Osimiry; Raimund Ubar; Sergei Kostin; Jaan Raik (NORCAS, 2016)

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. - Maksim Jenihhin; Giovanni Squillero; Thiago Santos Copetti; Valentin Tihhomirov; Sergei Kostin; Marco Gaudesi; Fabian Vargas 001; Jaan Raik; Matteo Sonza Reorda; Leticia Bolzani Poehls; Raimund Ubar; Guilherme Cardoso Medeiros (J. Electron. Test., 2016)

From online fault detection to fault management in Network-on-Chips: A ground-up approach. - Siavoosh Payandeh Azad; Behrad Niazmand; Karl Janson; Nevin George; Stephen Adeboye Oyeniran; Tsotne Putkaradze; Apneet Kaur; Jaan Raik; Gert Jervan; Raimund Ubar; Thomas Hollstein (DDECS, 2017)

A scalable technique to identify true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik (DDECS, 2017)

High-level test data generation for software-based self-test in microprocessors. - Adeboye Stephen Oyeniran; Artjom Jasnetski; Anton Tsertov; Raimund Ubar (MECO, 2017)

Automated software-based self-test generation for microprocessors. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov (MIXDES, 2017)

High-level test generation for processing elements in many-core systems. - Stephen Adeboye Oyeniran; Raimund Ubar; Siavoosh Payandeh Azad; Jaan Raik (ReCoSoC, 2017)

Modeling and simulation of circuits with shared structurally synthesized BDDs. - Raimund Ubar; Lembit Jürimägi; Jaan Raik; Vladimir Viies (Microprocess. Microsystems, 2017)

Combined pseudo-exhaustive and deterministic testing of array multipliers. - Adeboye Stephen Oyeniran; Siavoosh Payandeh Azad; Raimund Ubar (AQTR, 2018)

Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. - Siavoosh Payandeh Azad; Adeboye Stephen Oyeniran; Raimund Ubar (DDECS, 2018)

Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. - Adeboye Stephen Oyeniran; Siavoosh Payandeh Azad; Raimund Ubar (ISCAS, 2018)

Timing-critical path analysis with structurally synthesized BDDs. - Raimund Ubar; Lembit Jurimagi; Maksim Jenihhin; Jaan Raik; Niyi-Leigh Olugbenga; Vladimir Viies (MECO, 2018)

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. - Jaak Kousaar; Raimund Ubar; Sergei Kostin; Sergei Devadze; Jaan Raik (MIXDES, 2018)

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. - Lembit Jurimagi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Sergei Kostin (PATMOS, 2018)

Fast identification of true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Lembit Jürimägi (Microelectron. Reliab., 2018)

New categories of Safe Faults in a processor-based Embedded System. - Cemil Cem Gürsoy; Maksim Jenihhin; Adeboye Stephen Oyeniran; Davide Piumatti; Jaan Raik; Matteo Sonza Reorda; Raimund Ubar (DDECS, 2019)

True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. - Raimund Ubar; Lembit Jürimägi; Adeniyi Olanrewaju Adekoya; Maksim Jenihhin (DSD, 2019)

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (ETS, 2019)

Application Specific True Critical Paths Identification in Sequential Circuits. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Adeboye Stephen Oyeniran (IOLTS, 2019)

Mixed-level identification of fault redundancy in microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (LATS, 2019)

Equivalent Transformations of Structurally Synthesized BDDs and Applications. - Lembit Jürimägi; Raimund Ubar; Vladimir Viies (MECO, 2019)

High-Level Functional Test Generation for Microprocessor Modules. - Adeboye Stephen Oyeniran; Raimund Ubar (MIXDES, 2019)

Implementation-Independent Functional Test Generation for MSC Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC, 2019)

On Test Generation for Microprocessors for Extended Class of Functional Faults. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC (Selected Papers), 2019)

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (CoRR, 2019)

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (DSD, 2020)

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Raimund Ubar; Christian Sauer 001 (IOLTS, 2020)

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (J. Electron. Test., 2020)

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik (Microprocess. Microsystems, 2020)

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. - Maksim Jenihhin; Adeboye Stephen Oyeniran; Jaan Raik; Raimund Ubar (DSD, 2021)

High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. - Adeboye Stephen Oyeniran; Maksim Jenihhin; Jaan Raik; Raimund Ubar (ISVLSI, 2022)

Structural Decision Diagrams in Digital Test - Theory and Applications - Raimund Ubar; Jaan Raik; Maksim Jenihhin; Artur Jutman (Springer, 2024)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)