OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. - Birger Landwehr; Peter Marwedel; Rainer Dömer (EURO-DAC, 1994)

A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis. - Peter Marwedel; Steven Bashford; Rainer Dömer; Birger Landwehr; Ingolf Markhof (ED&TC, 1996)

Built-in chaining: introducing complex components into architectural synthesis. - Peter Marwedel; Birger Landwehr; Rainer Dömer (ASP-DAC, 1997)

IP-Centric Methodology and Specification Language. - Daniel Gajski; Rainer Dömer; Jianwen Zhu (DIPES, 1998)

Specification and Design of Embedded Systems. - Rainer Dömer; Daniel D. Gajski; Jianwen Zhu (Informationstechnik Tech. Inform., 1998)

Reuse and protection of intellectual property in the SpecC system. - Rainer Dömer; Daniel Gajski (ASP-DAC, 2000)

System-level modeling and design with the SpecC language. - Rainer Dömer (2000)

System Design - A Practical Guide with SpecC. - Andreas Gerstlauer; Rainer Dömer; Junyu Peng; Daniel D. Gajski (Springer, 2001)

The Formal Execution Semantics of SpecC. - Rainer Dömer; Andreas Gerstlauer; Wolfgang Müller 003 (ISSS, 2002)

Embedded software generation from system level design languages. - Haobo Yu; Rainer Dömer; Daniel Gajski (ASP-DAC, 2004)

System-level communication modeling for network-on-chip synthesis. - Andreas Gerstlauer; Dongwan Shin; Rainer Dömer; Daniel D. Gajski (ASP-DAC, 2005)

Automatic network generation for system-on-chip communication design. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (CODES+ISSS, 2005)

Abstract Communication Modeling. - Gunar Schirner; Rainer Dömer (IESS, 2005)

Automatic Generation of Communication Architectures. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (IESS, 2005)

Software and Driver Synthesis from Transaction Level Models. - Haobo Yu; Rainer Dömer; Daniel D. Gajski (IESS, 2005)

Accurate yet fast modeling of real-time communication. - Gunar Schirner; Rainer Dömer (CODES+ISSS, 2006)

Automatic generation of transaction level models for rapid design space exploration. - Dongwan Shin; Andreas Gerstlauer; Junyu Peng; Rainer Dömer; Daniel D. Gajski (CODES+ISSS, 2006)

Quantitative analysis of transaction level models for the AMBA bus. - Gunar Schirner; Rainer Dömer (DATE, 2006)

A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. - Ines Viskic; Rainer Dömer (DSD, 2006)

Fast and accurate transaction level models using result oriented modeling. - Gunar Schirner; Rainer Dömer (ICCAD, 2006)

Creating Explicit Communication in SoC Models Using Interactive Re-Coding. - Pramod Chandraiah; Junyu Peng; Rainer Dömer (ASP-DAC, 2007)

Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. - Gunar Schirner; Andreas Gerstlauer; Rainer Dömer (ASP-DAC, 2007)

Pointer re-coding for creating definitive MPSoC models. - Pramod Chandraiah; Rainer Dömer (CODES+ISSS, 2007)

Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. - Pramod Chandraiah; Rainer Dömer (DAC, 2007)

An Interactive Model Re-Coder for Efficient SoC Specification. - Pramod Chandraiah; Rainer Dömer (IESS, 2007)

Embedded Software Development in a System-Level Design Flow. - Gunar Schirner; Gautam Sachdeva; Andreas Gerstlauer; Rainer Dömer (IESS, 2007)

An Interactive Design Environment for C-based High-Level Synthesis. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel D. Gajski (IESS, 2007)

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. - Andreas Gerstlauer; Dongwan Shin; Junyu Peng; Rainer Dömer; Daniel Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM. - Gunar Schirner; Rainer Dömer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Automatic re-coding of reference code into structured and analyzable SoC models. - Pramod Chandraiah; Rainer Dömer (ASP-DAC, 2008)

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. - Gunar Schirner; Andreas Gerstlauer; Rainer Dömer (ASP-DAC, 2008)

Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. - Gunar Schirner; Rainer Dömer (DATE, 2008)

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. - Rainer Dömer; Andreas Gerstlauer; Junyu Peng; Dongwan Shin; Lukai Cai; Haobo Yu; Samar Abdi; Daniel D. Gajski (EURASIP J. Embed. Syst., 2008)

Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding. - Pramod Chandraiah; Rainer Dömer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. - Gunar Schirner; Rainer Dömer (ACM Trans. Embed. Comput. Syst., 2008)

An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. - Dongwan Shin; Andreas Gerstlauer; Rainer Dömer; Daniel Gajski (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. - Rainer Dömer; Andreas Gerstlauer; Wolfgang Müller 003 (ASP-DAC, 2009)

Programming MPSoC platforms: Road works ahead! - Rainer Leupers; Andras Vajda; Marco Bekooij; Soonhoi Ha; Rainer Dömer; Achim Nohl (DATE, 2009)

ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs. - Weiwei Chen 001; Rainer Dömer (IESS, 2009)

Efficient Modeling of Embedded Systems Using Computer-Aided Recoding. - Rainer Dömer (IESS, 2009)

A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance. - Ines Viskic; Rainer Dömer (IESS, 2009)

A fast heuristic scheduling algorithm for periodic ConcurrenC models. - Weiwei Chen 001; Rainer Dömer (ASP-DAC, 2010)

Computer-aided recoding for multi-core systems. - Rainer Dömer (ASP-DAC, 2010)

System-level development of embedded software. - Gunar Schirner; Andreas Gerstlauer; Rainer Dömer (ASP-DAC, 2010)

Panel Session - Who Is Closing the embedded software design gap? - Wolfgang Ecker; Pierre Bricaud; Rainer Dömer; Yossi Veller; Stefan Heinen; Jürgen Mössinger; Andreas von Schwerin (DATE, 2010)

ESL design and multi-core validation using the System-on-Chip Environment. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (HLDVT, 2010)

Fast and accurate processor models for efficient MPSoC design. - Gunar Schirner; Andreas Gerstlauer; Rainer Dömer (ACM Trans. Design Autom. Electr. Syst., 2010)

Multi-core parallel simulation of System-level Description Languages. - Rainer Dömer; Weiwei Chen 001; Xu Han 002; Andreas Gerstlauer (ASP-DAC, 2011)

Multicore Simulation of Transaction-Level Models Using the SoC Environment. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (IEEE Des. Test Comput., 2011)

An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation. - Weiwei Chen 001; Rainer Dömer (ASP-DAC, 2012)

Parallel discrete event simulation of Transaction Level Models. - Rainer Dömer; Weiwei Chen 001; Xu Han 002 (ASP-DAC, 2012)

Out-of-order parallel simulation for ESL design. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (DATE, 2012)

Eliminating race conditions in system-level models by using parallel simulation infrastructure. - Weiwei Chen 001; Che-Wei Chang; Xu Han 002; Rainer Dömer (HLDVT, 2012)

Computer-Aided Recoding to Create Structured and Analyzable System Models. - Pramod Chandraiah; Rainer Dömer (ACM Trans. Embed. Comput. Syst., 2012)

Optimized out-of-order parallel discrete event simulation using predictions. - Weiwei Chen 001; Rainer Dömer (DATE, 2013)

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component. - Takuya Azumi; Yasaman Samei Syahkal; Yuko Hara-Azumi; Hiroshi Oyama 002; Rainer Dömer (IESS, 2013)

Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories. - Che-Wei Chang; Rainer Dömer (IESS, 2013)

Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. - Xu Han 002; Weiwei Chen 001; Rainer Dömer (M-SCOPES, 2013)

Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. - Weiwei Chen 001; Xu Han 002; Che-Wei Chang; Rainer Dömer (IEEE Des. Test, 2013)

May-happen-in-parallel analysis based on segment graphs for safe ESL models. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (DATE, 2014)

Powermonitor: a versatile API for automated power-aware ESL design. - Yasaman Samei Syahkal; Rainer Dömer (FDL, 2014)

Automated estimation of power consumption for rapid system level design. - Yasaman Samei Syahkal; Rainer Dömer (IPCCC, 2014)

A program state machine based virtual processing model in SystemC. - Tim Schmidt; Kim Grüttner; Rainer Dömer; Achim Rettberg (SIGBED Rev., 2014)

Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. - Weiwei Chen 001; Xu Han 002; Che-Wei Chang; Guantao Liu; Rainer Dömer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories. - Che-Wei Chang; Rainer Dömer (ASP-DAC, 2015)

Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories. - Guantao Liu; Tim Schmidt; Rainer Dömer; Ajit Dingankar; Desmond Kirkpatrick (ASP-DAC, 2015)

May-happen-in-parallel analysis of ESL models using UPPAAL model checking. - Che-Wei Chang; Rainer Dömer (DATE, 2015)

A segment-aware multi-core scheduler for system C PDES. - Guantao Liu; Tim Schmidt; Rainer Dömer (HLDVT, 2016)

Automatic Generation of Thread Communication Graphs from SystemC Source Code. - Tim Schmidt; Guantao Liu; Rainer Dömer (SCOPES, 2016)

Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation. - Rainer Dömer (IEEE Embed. Syst. Lett., 2016)

Hybrid analysis of SystemC models for fast and accurate parallel simulation. - Tim Schmidt; Guantao Liu; Rainer Dömer (ASP-DAC, 2017)

Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation. - Tim Schmidt; Guantao Liu; Rainer Dömer (DAC, 2017)

Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study. - Zhongqi Cheng; Tim Schmidt; Guantao Liu; Rainer Dömer (HLDVT, 2017)

Parallel Simulation. - Rainer Dömer; Guantao Liu; Tim Schmidt (Handbook of Hardware/Software Codesign, 2017)

Introduction to Hardware/Software Codesign. - Soonhoi Ha; Jürgen Teich; Christian Haubelt; Michael Glaß; Tulika Mitra; Rainer Dömer; Petru Eles; Aviral Shrivastava; Andreas Gerstlauer; Shuvra S. Bhattacharyya (Handbook of Hardware/Software Codesign, 2017)

SCE: System-on-Chip Environment. - Gunar Schirner; Andreas Gerstlauer; Rainer Dömer (Handbook of Hardware/Software Codesign, 2017)

Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. - Tim Schmidt; Zhongqi Cheng; Rainer Dömer (DATE, 2018)

SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation. - Zhongqi Cheng; Tim Schmidt; Rainer Dömer (FDL, 2018)

An Untimed SystemC Model of GoogLeNet. - Emad Malekzadeh Arasteh; Rainer Dömer (IESS, 2019)

Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models. - Zhongqi Cheng; Rainer Dömer (ACM Trans. Embed. Comput. Syst., 2019)

Event Delivery using Prediction for Faster Parallel SystemC Simulation. - Zhongqi Cheng; Emad Malekzadeh Arasteh; Rainer Dömer (ASP-DAC, 2020)

Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES. - Daniel Mendoza; Zhongqi Cheng; Emad Malekzadeh Arasteh; Rainer Dömer (DATE, 2020)

Pushing the Limits of Parallel Discrete Event Simulation for SystemC. - Rainer Dömer; Zhongqi Cheng; Daniel Mendoza; Emad Malekzadeh Arasteh (A Journey of Embedded and Cyber-Physical Systems, 2021)

Improving Parallelism in System Level Models by Assessing PDES Performance. - Emad Malekzadeh Arasteh; Rainer Dömer (FDL, 2021)

Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation. - Zhongqi Cheng; Tim Schmidt; Rainer Dömer (Int. J. Parallel Program., 2021)

Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells. - Vivek Govindasamy; Emad Malekzadeh Arasteh; Rainer Dömer (IESS, 2022)

Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0. - Yutong Wang; Arya Daroui; Rainer Dömer (IESS, 2022)

Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells. - Vivek Govindasamy; Rainer Dömer (FDL, 2023)

Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. - Lars Luchterhandt; Tom Nellius; Robert Beck; Rainer Dömer; Pascal Kneuper; Wolfgang Mueller; Babak Sadiye (MBMV, 2023)

BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0. - Emad Malekzadeh Arasteh; Vivek Govindasamy; Rainer Dömer (DATE, 2024)

Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention. - Emad Malekzadeh Arasteh; Rainer Dömer (ACM Trans. Embed. Comput. Syst., 2024)