A RISC Processor with Extended Forwarding. - Gert Markwardt; Günter Kemnitz; Rainer G. Spallek (ARCS, 1997)

Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen. - Achim Gratz; Rainer G. Spallek (MMB (Kurzbeiträge), 1997)

Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. - Sergej Sawitzki; Achim Gratz; Rainer G. Spallek (FPL, 1998)

Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen. - Raimar Falke; Michael Peter; Achim Gratz; Rainer G. Spallek (Java-Informations-Tage, 1998)

A Concept for an Evaluation Framework for Reconfigurable Systems. - Sergej Sawitzki; Rainer G. Spallek (FPL, 1999)

Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. - Steffen Köhler; Sergej Sawitzki; Achim Gratz; Rainer G. Spallek (IPPS/SPDP Workshops, 1999)

Formal Verification for Microprocessors with Extendable Instruction Set. - Sergej Sawitzki; Rainer G. Spallek; Jens Schönherr; Bernd Straube (ASAP, 2000)

Formal Verification of a Reconfigurable Microprocessor. - Sergej Sawitzki; Jens Schönherr; Rainer G. Spallek; Bernd Straube (FPL, 2000)

Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. - Sergej Sawitzki; Steffen Köhler; Rainer G. Spallek; Jörg Schneider; S. Rülke (MBMV, 2000)

Prototyping Framework for Reconfigurable Processors. - Sergej Sawitzki; Steffen Köhler; Rainer G. Spallek (FPL, 2001)

A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. - Sebastian Friebe; Steffen Köhler; Rainer G. Spallek; Henrik Juhr; Klaus Künanz (FPL, 2002)

Improving Code Efficiency for Reconfigurable VLIW Processors. - Steffen Köhler; Jens Braunes; Sergej Sawitzki; Rainer G. Spallek (IPDPS, 2002)

Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. - Sergej Sawitzki; Rainer G. Spallek (FPL, 2003)

RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. - Jens Braunes; Steffen Köhler; Rainer G. Spallek (ARCS, 2004)

RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. - Thomas Preußer; Steffen Köhler; Rainer G. Spallek (ESA/VLSI, 2004)

Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. - Steffen Köhler; Jens Braunes; Thomas Preußer; Martin Zabel; Rainer G. Spallek (FPL, 2004)

Ein Zwischenformat-Profiler für das RECAST-Framework. - Jens Braunes; Steffen Köhler; Annett Königsmann; Rainer G. Spallek (ARCS Workshops, 2005)

Design space exploration of coarse-grain reconfigurable DSPs. - Martin Zabel; Steffen Köhler; Martin Zimmerling; Thomas B. Preußer; Rainer G. Spallek (ReConFig, 2005)

A Compiler-Oriented Architecture Description for Reconfigurable Systems. - Jens Braunes; Rainer G. Spallek (ARC, 2006)

Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. - Steffen Köhler; Martin Zimmerling; Martin Zabel; Rainer G. Spallek (ARCS Workshops, 2006)

Analysis of a Fully-Scalable Digital Fractional Clock Divider. - Thomas B. Preußer; Rainer G. Spallek (ASAP, 2006)

Implementation of Architecture Concepts for Hardware Agent Systems. - Jörg Schneider; Marcel Naggatz; Rainer G. Spallek (CIT, 2007)

Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. - Martin Zabel; Thomas B. Preußer; Peter Reichel; Rainer G. Spallek (DSD, 2007)

Enabling constant-time interface method dispatch in embedded Java processors. - Thomas Preußer; Martin Zabel; Rainer G. Spallek (JTRES, 2007)

Bump-pointer method caching for embedded Java processors. - Thomas Preußer; Martin Zabel; Rainer G. Spallek (JTRES, 2007)

Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study. - Steffen Köhler; Jan Schirok; Jens Braunes; Rainer G. Spallek (ARC, 2008)

Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. - Thomas Preußer; Rainer G. Spallek (ESA, 2008)

Generating the trace qualification configuration for MCDS from a high level language. - Jens Braunes; Rainer G. Spallek (DATE, 2009)

Mapping basic prefix computations to fast carry-chain structures. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2009)

High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. - Martin Zabel; Thomas B. Preußer; Rainer G. Spallek (MBMV, 2009)

An Embedded GC Module with Support for Multiple Mutators and Weak References. - Thomas B. Preußer; Peter Reichel; Rainer G. Spallek (ARCS, 2010)

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2010)

Solving Sudokus through an incidence matrix on an FPGA. - Michael Dittrich; Thomas B. Preußer; Rainer G. Spallek (FPT, 2010)

Application requirements and efficiency of embedded Java bytecode multi-cores. - Martin Zabel; Rainer G. Spallek (JTRES, 2010)

Accelerating Computations on FPGA Carry Chains by Operand Compaction. - Thomas B. Preußer; Martin Zabel; Rainer G. Spallek (IEEE Symposium on Computer Arithmetic, 2011)

Next-generation massively parallel short-read mapping on FPGAs. - Oliver Knodel; Thomas B. Preußer; Rainer G. Spallek (ASAP, 2011)

The Java Virtual Machine in retargetable, high-performance instruction set simulation. - Marco Kaufmann; Matthias Häsing; Thomas Preußer; Rainer G. Spallek (PPPJ, 2011)

Short-Read Mapping by a Systolic Custom FPGA Computation. - Thomas B. Preußer; Oliver Knodel; Rainer G. Spallek (FCCM, 2012)

Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace. - Kai-Uwe Irrgang; Rainer G. Spallek (IEEE GSC, 2012)

Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. - Martin Zabel; Thomas B. Preußer; Rainer G. Spallek (JTRES, 2012)

Integration of a multi-FPGA system in a common cluster environment. - Oliver Knodel; Rainer G. Spallek (FPL, 2013)

Weasel: A platform-independent streaming-optimized SATA controller. - Patrick Lehmann 001; Thomas Frank; Oliver Knodel; Steffen Köhler; Thomas B. Preußer; Rainer G. Spallek (FPL, 2013)

Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures. - Oliver Knodel; Andy Georgi; Patrick Lehmann 001; Wolfgang E. Nagel; Rainer G. Spallek (ICPP, 2013)

Superblock compilation and other optimization techniques for a Java-based DPT machine emulator. - Marco Kaufmann; Rainer G. Spallek (VEE, 2013)

Educating hardware design - From primary school children to postgraduate engineers. - Oliver Knodel; Martin Zabel; Patrick Lehmann 001; Rainer G. Spallek (FPL, 2014)

Ready PCIe data streaming solutions for FPGAs. - Thomas B. Preußer; Rainer G. Spallek (FPL, 2014)

PoC-align: An open-source alignment accelerator using FPGAs. - Thomas B. Preußer; Oliver Knodel; Rainer G. Spallek (ReConFig, 2014)

Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. - Oliver Knodel; Rainer G. Spallek (DSD, 2015)

Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. - Kai-Uwe Irrgang; Thomas B. Preußer; Rainer G. Spallek (GI-Jahrestagung, 2015)

RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment. - Oliver Knodel; Rainer G. Spallek (CoRR, 2015)

RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models. - Oliver Knodel; Patrick Lehmann 001; Rainer G. Spallek (CLOUD, 2016)

The portable open-source IP core and utility library PoC. - Thomas B. Preußer; Martin Zabel; Patrick Lehmann 001; Rainer G. Spallek (ReConFig, 2016)

Migration of long-running Tasks between Reconfigurable Resources using Virtualization. - Oliver Knodel; Paul R. Genssler; Rainer G. Spallek (SIGARCH Comput. Archit. News, 2016)

A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. - Paul R. Genßler; Oliver Knodel; Rainer G. Spallek (GI-Jahrestagung, 2017)

First Workshop on Hardware Defined Programming - HDP. - Oliver Knodel; Steffen Köhler; Marko Rößler; Rainer G. Spallek (GI-Jahrestagung, 2017)

Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. - Steffen Köhler; Rainer G. Spallek (GI-Jahrestagung, 2017)

Research and implementation of efficient parallel processing of big data at TELBE user facility. - Mohammed Bawatna; Bertram Green; Sergey Kovalev; Jan-Christoph Deinert; Oliver Knodel; Rainer G. Spallek (SummerSim, 2019)

Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture. - Mohammed Bawatna; Oliver Knodel; Rainer G. Spallek (CSOC (3), 2020)

Possibilities and Challenges for Reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific Applications. - Mohammed Bawatna; Oliver Knodel; Rainer G. Spallek (SDS, 2020)