A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. - Rainer Kreienkamp; Ulrich Langmann; Christoph Zimmermann; Takuma Aoyama (CICC, 2003)

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. - Rainer Kreienkamp; Ulrich Langmann; Christoph Zimmermann; Takuma Aoyama; Hubert Siedhoff (IEEE J. Solid State Circuits, 2005)

Interferer performance dependency on analog-digital-conversion of GNSS-class signals in GPS receivers. - Christoph Schultz; Markus Hammes; Rainer Kreienkamp; Lars Lemke; Stefan van Waasen (ICECS, 2010)

A double-mixing sampling receiver concept to enable GNSS-L1/L5 double-band reception. - Christoph Schultz; Christian Duerdodt; Markus Hammes; Rainer Kreienkamp (SSD, 2012)