Specification and verification of VHDL-based system-level hardware designs. - Werner Damm; Bernhard Josko; Rainer Schlör (Specification and validation methods, 1993)

A net-based semantics for VHDL. - Werner Damm; Bernhard Josko; Rainer Schlör (EURO-DAC, 1993)

VHDL/S - integrating statecharts, timing diagrams, and VHDL. - Johannes Helbig; Rainer Schlör; Werner Damm; Gert Döhmen; Peter Kelb (Microprocess. Microprogramming, 1993)

Interface Controller Synthesis from Requirement Specifications. - Franz Korf; Rainer Schlör (EDAC-ETC-EUROASIC, 1994)

Verification of a production cell controller using symbolic timing diagrams. - Rainer Schlör; Franz Korf (EURO-DAC, 1995)

Statecharts. - Werner Damm; Hardi Hungar; Peter Kelb; Rainer Schlör (Formal Development of Reactive Systems, 1995)

Symbolic Timing Diagrams. - Franz Korf; Rainer Schlör (Formal Development of Reactive Systems, 1995)

Hardware synthesis from requirement specifications. - Konrad Feyerabend; Rainer Schlör (EURO-DAC, 1996)

Using a Visual Formalism for Design Verification in Industrial Environments. - Rainer Schlör; Bernhard Josko; Dieter Werth (Services and Visualization: Towards User-Friendly Design, 1998)

Symbolic timing diagrams: a visual formalism for model verification. - Rainer Schlör (2002)

Cost-Efficient Worst-Case Execution Time Analysis in Industrial Practice. - Jan Staschulat; Jörn-Christian Braam; Rolf Ernst; Thomas Rambow; Rainer Schlör; Rainer Busch (ISoLA, 2006)

Analysis Using the Business Support Matrix: Elaborating Potential for Improving Application Landscapes in Logistics. - Rainer Schlör; Jürgen Jung (EDOC Workshops, 2018)