Design and integration methods for a multi-threaded dual core 65nm Xeon® processor. - Raj Varada; Mysore Sriram; Kris Chou; James Guzzo (ICCAD, 2006)

SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor. - Raj Varada; Simon Tarn; John Benoit; Kris Chou (SoCC, 2006)

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang; Brian S. Cherkauer; Jason Stinson; John Benoit; Raj Varada; Justin Leung; Rahul Dilip Limaye; Sujal Vora (IEEE J. Solid State Circuits, 2007)

Power reduction techniques for an 8-core xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (ESSCIRC, 2009)

A 45nm 8-core enterprise Xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli (ISSCC, 2009)

A 45 nm 8-Core Enterprise Xeon¯ Processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (IEEE J. Solid State Circuits, 2010)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)