High Speed Controllable Inverter for Adder-Subtractor in QCA. - Marshal Raj; Raja Sekar Kumaresan; Gopalakrishnan Lakshminarayanan (ICCCNT, 2019)

Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique. - Marshal Raj; Raja Sekar Kumaresan; Gopalakrishnan Lakshminarayanan (ICCCNT, 2019)

Area-Efficient D-Flip Flop and XOR in QCA. - Raja Sekar Kumaresan; Marshal Raj; Gopalakrishnan Lakshminarayanan (ICCCNT, 2020)

Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs. - Anantharaj Thalaimalai Vanaraj; Raja Sekar Kumaresan; Marshal Raj; G. Lakshminarayanan (ICCCNT, 2022)

Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs. - Anantharaj Thalaimalai Vanaraj; Raja Sekar Kumaresan; Marshal Raj; Anand Venkitachalam; G. Lakshminarayanan (ICCCNT, 2022)

Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata. - Marshal Raj; Raja Sekar Kumaresan; G. Lakshminarayanan (IEEE Des. Test, 2022)

High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata. - Raja Sekar Kumaresan; Marshal Raj; G. Lakshminarayanan (IEEE Embed. Syst. Lett., 2022)

Framework for QCA Layout Generation and Rules for Rotated Cell Design. - Raja Sekar Kumaresan; Marshal Raj; Gopalakrishnan Lakshminarayanan (J. Circuits Syst. Comput., 2023)