3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. - John J. Wuu; Rahul Agarwal; Michael Ciraula; Carl Dietz; Brett Johnson; Dave Johnson 002; Russell Schreiber; Raja Swaminathan; Will Walker; Samuel Naffziger (ISSCC, 2022)

The Next Era for Chiplet Innovation. - Gabriel H. Loh; Raja Swaminathan (DATE, 2023)

AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture. - Raja Swaminathan; Michael J. Schulte; Brett Wilkerson; Gabriel H. Loh; Alan Smith 003; Norman James (VLSI Technology and Circuits, 2023)

Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. - Alan Smith 003; Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Samuel Naffziger; Mike Mantor; Nathan Kalyanasundharam; Vamsi Alla; Nicholas Malaya; Joseph L. Greathouse; Eric Chapman; Raja Swaminathan (ISCA, 2024)

11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems. - Alan Smith; Eric Chapman; Chintan Patel; Raja Swaminathan; John J. Wuu; Tyrone Huang; Wonjun Jung; Alexander Kaganov; Hugh McIntyre; Ramon Mangaser (ISSCC, 2024)

AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. - Alan Smith 003; Gabriel H. Loh; John J. Wuu; Samuel Naffziger; Tyrone Huang; Hugh McIntyre; Ramon Mangaser; Wonjun Jung; Raja Swaminathan (VLSI Technology and Circuits, 2024)

Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator. - Alan Smith 003; Gabriel H. Loh; Samuel Naffziger; John J. Wuu; Nathan Kalyanasundharam; Eric Chapman; Raja Swaminathan; Tyrone Huang; Wonjun Jung; Alexander Kaganov; Hugh McIntyre; Ramon Mangaser (IEEE Micro, 2025)