Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. - Rajamani Sethuram; Seongmoon Wang; Srimat T. Chakradhar; Michael L. Bushnell (ATS, 2006)

A Neural Net Branch Predictor to Reduce Power. - Rajamani Sethuram; Omar I. Khan; Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2007)

Zero Cost Test Point Insertion Technique for Structured ASICs. - Rajamani Sethuram; Seongmoon Wang; Srimat T. Chakradhar; Michael L. Bushnell (VLSI Design, 2007)

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. - Rajamani Sethuram; Michael L. Bushnell; Vishwani D. Agrawal (VTS, 2008)

Gating internal nodes to reduce power during scan shift. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)

Scan Shift Power Reduction by Gating Internal Nodes. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (J. Low Power Electron., 2010)

Trace Buffer-Based Silicon Debug with Lossless Compression. - Sandesh Prabhakar; Rajamani Sethuram; Michael S. Hsiao (VLSI Design, 2011)

Leakage power profiling and leakage power reduction using DFT hardware. - Rajamani Sethuram; Karim Arabi; Mohamed H. Abu-Rahma (VTS, 2011)