Effect of Power Optimizations on Soft Error Rate. - Vijay Degalahal; Rajaraman Ramanarayanan; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin (VLSI-SoC (Selected Papers), 2003)

The Effect of Threshold Voltages on the Soft Error Rate. - Vijay Degalahal; Rajaraman Ramanarayanan; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin (ISQED, 2004)

A Process Scheduler-Based Approach to NoC Power Management. - Feihui Li; Guilin Chen; Mahmut T. Kandemir; Ozcan Ozturk 001; Mustafa Karaköy; Rajaraman Ramanarayanan; Balaji Vaidyanathan (VLSI Design, 2007)

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. - Liping Xue; Mahmut T. Kandemir; Guilin Chen; Feihui Li; Ozcan Ozturk 001; Rajaraman Ramanarayanan; Balaji Vaidyanathan (VLSI Design, 2007)

A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. - Rajaraman Ramanarayanan; Sanu Mathew; Vasantha Erraguntla; Ram Krishnamurthy 001; Shay Gueron (VLSI Design, 2008)

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. - Rajaraman Ramanarayanan; Vijay Degalahal; Krishnan Ramakrishnan; Jungsub Kim; Vijaykrishnan Narayanan; Yuan Xie 001; Mary Jane Irwin; Kenan Unlu (IEEE Trans. Dependable Secur. Comput., 2009)

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. - Rajaraman Ramanarayanan; Sanu Mathew; Farhana Sheikh; Suresh Srinivasan; Amit Agarwal 001; Steven Hsu; Himanshu Kaul; Mark A. Anders 001; Vasantha Erraguntla; Ram Krishnamurthy 001 (ESSCIRC, 2010)

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. - Amit Agarwal 001; Sanu Mathew; Steven Hsu; Mark A. Anders 001; Himanshu Kaul; Farhana Sheikh; Rajaraman Ramanarayanan; Suresh Srinivasan; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2010)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

Split-Path Fused Floating Point Multiply Accumulate (FPMAC). - Suresh Srinivasan; Ketan Bhudiya; Rajaraman Ramanarayanan; P. Sahit Babu; Tiju Jacob; Sanu Mathew; Ram Krishnamurthy 001; Vasantha Erraguntla (IEEE Symposium on Computer Arithmetic, 2013)