Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. - Rajeev Balasubramonian; David H. Albonesi; Alper Buyuktosunoglu; Sandhya Dwarkadas (MICRO, 2000)

Dynamically allocating processor resources between nearby and distant ILP. - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (ISCA, 2001)

Reducing the complexity of the register file in dynamic superscalar processors. - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (MICRO, 2001)

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. - Steve Dropsho; Alper Buyuktosunoglu; Rajeev Balasubramonian; David H. Albonesi; Sandhya Dwarkadas; Greg Semeraro; Grigorios Magklis; Michael L. Scott (IEEE PACT, 2002)

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. - Greg Semeraro; Grigorios Magklis; Rajeev Balasubramonian; David H. Albonesi; Sandhya Dwarkadas; Michael L. Scott (HPCA, 2002)

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (ISCA, 2003)

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. - Rajeev Balasubramonian; Viji Srinivasan; Sandhya Dwarkadas; Alper Buyuktosunoglu (PACS, 2003)

Dynamically Tuning Processor Resources with Adaptive Processing. - David H. Albonesi; Rajeev Balasubramonian; Steve Dropsho; Sandhya Dwarkadas; Eby G. Friedman; Michael C. Huang 001; Volkan Kursun; Grigorios Magklis; Michael L. Scott; Greg Semeraro; Pradip Bose; Alper Buyuktosunoglu; et al. (Computer, 2003)

A Dynamically Tunable Memory Hierarchy. - Rajeev Balasubramonian; David H. Albonesi; Alper Buyuktosunoglu; Sandhya Dwarkadas (IEEE Trans. Computers, 2003)

Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. - Rajeev Balasubramonian (ICS, 2004)

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. - Rajeev Balasubramonian; Naveen Muralimanohar; Karthik Ramani; Venkatanand Venkatachalapathy (HPCA, 2005)

Interconnect-Aware Coherence Protocols for Chip Multiprocessors. - Liqun Cheng; Naveen Muralimanohar; Karthik Ramani; Rajeev Balasubramonian; John B. Carter (ISCA, 2006)

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. - Naveen Muralimanohar; Karthik Ramani; Rajeev Balasubramonian (ISPASS, 2006)

Leveraging Wire Properties at the Microarchitecture Level. - Rajeev Balasubramonian; Naveen Muralimanohar; Karthik Ramani; Liqun Cheng; John B. Carter (IEEE Micro, 2006)

Interconnect design considerations for large NUCA caches. - Naveen Muralimanohar; Rajeev Balasubramonian (ISCA, 2007)

Leveraging 3D Technology for Improved Reliability. - Niti Madan; Rajeev Balasubramonian (MICRO, 2007)

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. - Naveen Muralimanohar; Rajeev Balasubramonian; Norman P. Jouppi (MICRO, 2007)

Understanding the Impact of 3D Stacked Layouts on ILP. - Manu Awasthi; Vivek Venkatesan; Rajeev Balasubramonian (J. Instr. Level Parallelism, 2007)

Power Efficient Approaches to Redundant Multithreading. - Niti Madan; Rajeev Balasubramonian (IEEE Trans. Parallel Distributed Syst., 2007)

Scalable and reliable communication for hardware transactional memory. - Seth H. Pugsley; Manu Awasthi; Niti Madan; Naveen Muralimanohar; Rajeev Balasubramonian (PACT, 2008)

Architecting Efficient Interconnects for Large Caches with CACTI 6.0. - Naveen Muralimanohar; Rajeev Balasubramonian; Norman P. Jouppi (IEEE Micro, 2008)

Non-uniform power access in large caches with low-swing wires. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HiPC, 2009)

Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. - Manu Awasthi; Kshitij Sudan; Rajeev Balasubramonian; John B. Carter (HPCA, 2009)

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. - Niti Madan; Li Zhao 002; Naveen Muralimanohar; Aniruddha N. Udipi; Rajeev Balasubramonian; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell (HPCA, 2009)

OS execution on multi-cores: is out-sourcing worthwhile? - David W. Nellans; Rajeev Balasubramonian; Erik Brunvand (ACM SIGOPS Oper. Syst. Rev., 2009)

Handling the problems and opportunities posed by multiple on-chip memory controllers. - Manu Awasthi; David W. Nellans; Kshitij Sudan; Rajeev Balasubramonian; Al Davis (PACT, 2010)

SWEL: hardware cache coherence protocols to map shared data onto shared caches. - Seth H. Pugsley; Josef B. Spjut; David W. Nellans; Rajeev Balasubramonian (PACT, 2010)

Micro-pages: increasing DRAM efficiency with locality-aware data placement. - Kshitij Sudan; Niladrish Chatterjee; David W. Nellans; Manu Awasthi; Rajeev Balasubramonian; Al Davis (ASPLOS, 2010)

CHOP: Adaptive filter-based DRAM caching for CMP server platforms. - Xiaowei Jiang; Niti Madan; Li Zhao 002; Mike Upton; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell; Yan Solihin; Rajeev Balasubramonian (HPCA, 2010)

Towards scalable, energy-efficient, bus-based on-chip networks. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HPCA, 2010)

Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality. - David W. Nellans; Kshitij Sudan; Erik Brunvand; Rajeev Balasubramonian (ISCA Workshops, 2010)

Rethinking DRAM design and organization for energy-constrained multi-cores. - Aniruddha N. Udipi; Naveen Muralimanohar; Niladrish Chatterjee; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2010)

Hardware prediction of OS run-length for fine-grained resource customization. - David W. Nellans; Kshitij Sudan; Rajeev Balasubramonian; Erik Brunvand (ISPASS, 2010)

Prediction Based DRAM Row-Buffer Management in the Many-Core Era. - Manu Awasthi; David W. Nellans; Rajeev Balasubramonian; Al Davis (PACT, 2011)

Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures. - Gagandeep S. Sachdev; Kshitij Sudan; Mary W. Hall; Rajeev Balasubramonian (PACT, 2011)

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2011)

CHOP: Integrating DRAM Caches for CMP Server Platforms. - Xiaowei Jiang; Niti Madan; Li Zhao 002; Mike Upton; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell; Yan Solihin; Rajeev Balasubramonian (IEEE Micro, 2011)

Buses and Crossbars. - Rajeev Balasubramonian; Timothy Mark Pinkston (Encyclopedia of Parallel Computing, 2011)

Multi-Core Cache Hierarchies - Rajeev Balasubramonian; Norman P. Jouppi; Naveen Muralimanohar (Morgan & Claypool Publishers, 2011)

Optimizing datacenter power with memory system levers for guaranteed quality-of-service. - Kshitij Sudan; Sadagopan Srinivasan; Rajeev Balasubramonian; Ravi R. Iyer 001 (PACT, 2012)

Efficient scrub mechanisms for error-prone emerging memories. - Manu Awasthi; Manjunath Shevgoor; Kshitij Sudan; Bipin Rajendran; Rajeev Balasubramonian; Viji Srinivasan (HPCA, 2012)

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. - Niladrish Chatterjee; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (HPCA, 2012)

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2012)

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access. - Niladrish Chatterjee; Manjunath Shevgoor; Rajeev Balasubramonian; Al Davis; Zhen Fang 002; Ramesh Illikkal; Ravi R. Iyer 001 (MICRO, 2012)

Managing Data Placement in Memory Systems with Multiple Memory Controllers. - Manu Awasthi; David W. Nellans; Kshitij Sudan; Rajeev Balasubramonian; Al Davis (Int. J. Parallel Program., 2012)

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. - Kshitij Sudan; Saisanthosh Balakrishnan; Sean Lie; Min Xu; Dhiraj Mallick; Gary Lauterbach; Rajeev Balasubramonian (HPCA, 2013)

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. - Manjunath Shevgoor; Jung-Sik Kim; Niladrish Chatterjee; Rajeev Balasubramonian; Al Davis; Aniruddha N. Udipi (MICRO, 2013)

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. - Seth H. Pugsley; Zeshan Chishti; Chris Wilkerson; Peng-fei Chuang; Robert L. Scott; Aamer Jaleel; Shih-Lien Lu; Kingsum Chow; Rajeev Balasubramonian (HPCA, 2014)

MemZip: Exploring unconventional benefits from memory compression. - Ali Shafiee; Meysam Taassori; Rajeev Balasubramonian; Al Davis (HPCA, 2014)

Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller. - Akhila Gundu; Gita Sreekumar; Ali Shafiee; Seth H. Pugsley; Hardik B. Jain; Rajeev Balasubramonian; Mohit Tiwari (HASP@ISCA, 2014)

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. - Seth H. Pugsley; Jeffrey Jestes; Huihui Zhang; Rajeev Balasubramonian; Vijayalakshmi Srinivasan; Alper Buyuktosunoglu; Al Davis; Feifei Li 001 (ISPASS, 2014)

Managing DRAM Latency Divergence in Irregular GPGPU Applications. - Niladrish Chatterjee; Mike O'Connor; Gabriel H. Loh; Nuwan Jayasena; Rajeev Balasubramonian (SC, 2014)

Near-Data Processing: Insights from a MICRO-46 Workshop. - Rajeev Balasubramonian; Jichuan Chang; Troy Manning; Jaime H. Moreno; Richard Murphy; Ravi Nair; Steven Swanson (IEEE Micro, 2014)

Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. - Seth H. Pugsley; Jeffrey Jestes; Rajeev Balasubramonian; Vijayalakshmi Srinivasan; Alper Buyuktosunoglu; Al Davis; Feifei Li 001 (IEEE Micro, 2014)

Overcoming the challenges of crossbar resistive memory architectures. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Rajeev Balasubramonian; Tao Zhang 032; Shimeng Yu; Yuan Xie 001 (HPCA, 2015)

Fixed-function hardware sorting accelerators for near data MapReduce execution. - Seth H. Pugsley; Arjun Deb; Rajeev Balasubramonian; Feifei Li 001 (ICCD, 2015)

Improving memristor memory with sneak current sharing. - Manjunath Shevgoor; Naveen Muralimanohar; Rajeev Balasubramonian; Yoocharn Jeon (ICCD, 2015)

Avoiding information leakage in the memory controller with fixed service policies. - Ali Shafiee; Akhila Gundu; Manjunath Shevgoor; Rajeev Balasubramonian; Mohit Tiwari (MICRO, 2015)

Efficiently prefetching complex address patterns. - Manjunath Shevgoor; Sahil Koladiya; Rajeev Balasubramonian; Chris Wilkerson; Seth H. Pugsley; Zeshan Chishti (MICRO, 2015)

Enabling technologies for memory compression: Metadata, mapping, and prediction. - Arjun Deb; Paolo Faraboschi; Ali Shafiee; Naveen Muralimanohar; Rajeev Balasubramonian; Robert Schreiber (ICCD, 2016)

Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system. - Meysam Taassori; Ali Shafiee; Rajeev Balasubramonian (ICCD, 2016)

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. - Ali Shafiee; Anirban Nag; Naveen Muralimanohar; Rajeev Balasubramonian; John Paul Strachan; Miao Hu 002; R. Stanley Williams; Vivek Srikumar (ISCA, 2016)

Addressing service interruptions in memory with thread-to-rank assignment. - Manjunath Shevgoor; Rajeev Balasubramonian; Niladrish Chatterjee; Jung-Sik Kim (ISPASS, 2016)

Near-Data Processing [Guest editors' introduction]. - Rajeev Balasubramonian; Boris Grot (IEEE Micro, 2016)

Introspective Computing. - Karl Taht; Rajeev Balasubramonian (PACT, 2017)

INXS: Bridging the throughput and energy gap for spiking neural networks. - Surya Narayanan; Ali Shafiee; Rajeev Balasubramonian (IJCNN, 2017)

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. - Rajeev Balasubramonian; Andrew B. Kahng; Naveen Muralimanohar; Ali Shafiee; Vaishnav Srinivas (ACM Trans. Archit. Code Optim., 2017)

VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures. - Meysam Taassori; Ali Shafiee; Rajeev Balasubramonian (ASPLOS, 2018)

Moving CNN Accelerator Computations Closer to Data. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian (EMC2@ASPLOS, 2018)

A Case for Dynamic Activation Quantization in CNNs. - Karl Taht; Surya Narayanan; Rajeev Balasubramonian (EMC2@ASPLOS, 2018)

Secure DIMM: Moving ORAM Primitives Closer to Memory. - Ali Shafiee; Rajeev Balasubramonian; Mohit Tiwari; Feifei Li 001 (HPCA, 2018)

An MLP-aware leakage-free memory controller. - Andrew Vuong; Ali Shafiee; Meysam Taassori; Rajeev Balasubramonian (HASP@ISCA, 2018)

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. - Anirban Nag; Ali Shafiee; Rajeev Balasubramonian; Vivek Srikumar; Naveen Muralimanohar (CoRR, 2018)

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. - Anirban Nag; Rajeev Balasubramonian; Vivek Srikumar; Ross Walker 001; Ali Shafiee; John Paul Strachan; Naveen Muralimanohar (IEEE Micro, 2018)

ρ: Relaxed Hierarchical ORAM. - Chandrasekhar Nagarajan; Ali Shafiee; Rajeev Balasubramonian; Mohit Tiwari (ASPLOS, 2019)

The POP Detector: A Lightweight Online Program Phase Detection Framework. - Karl Taht; James Greensky; Rajeev Balasubramonian (ISPASS, 2019)

Wire-Aware Architecture and Dataflow for CNN Accelerators. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. - Anirban Nag; C. N. Ramachandra; Rajeev Balasubramonian; Ryan Stutsman; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

Innovations in the Memory System - Rajeev Balasubramonian (Morgan & Claypool Publishers, 2019)

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. - Surya Narayanan; Karl Taht; Rajeev Balasubramonian; Edouard Giacomin; Pierre-Emmanuel Gaillardon (ISCA, 2020)

Compact Leakage-Free Support for Integrity and Reliability. - Meysam Taassori; Rajeev Balasubramonian; Siddhartha Chhabra; Alaa R. Alameldeen; Manjula Peddireddy; Rajat Agarwal; Ryan Stutsman (ISCA, 2020)

ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis. - C. N. Ramachandra; Anirban Nag; Rajeev Balasubramonian; Gurpreet S. Kalsi; Kamlesh R. Pillai; Sreenivas Subramoney (FCCM, 2021)

Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication. - Adarsh Patil 002; Vijay Nagarajan; Rajeev Balasubramonian; Nicolai Oswald (ISCA, 2021)

OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations. - Anirban Nag; Rajeev Balasubramonian (MICRO, 2021)

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. - Sumanth Gudaparthi; Sarabjeet Singh; Surya Narayanan; Rajeev Balasubramonian; Visvesh Sathe 001 (HPCA, 2022)

Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract). - Zhao Chang; Dong Xie 001; Feifei Li 001; Jeff M. Phillips; Rajeev Balasubramonian (ICDE, 2022)

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. - Amlan Ganguly; Sergi Abadal; Ishan G. Thakkar; Natalie Enright Jerger; Marc D. Riedel; Masoud Babaie; Rajeev Balasubramonian; Abu Sebastian; Sudeep Pasricha; Baris Taskin (IEEE Micro, 2022)

Efficient Oblivious Query Processing for Range and kNN Queries. - Zhao Chang; Dong Xie 001; Feifei Li 001; Jeff M. Phillips; Rajeev Balasubramonian (IEEE Trans. Knowl. Data Eng., 2022)

XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays. - Sarabjeet Singh; Xiong Fan; Ananth Krishna Prasad; Lin Jia; Anirban Nag; Rajeev Balasubramonian; Mahdi Nazm Bojnordi; Elaine Shi (IEEE Micro, 2023)

PATHFINDER: Practical Real-Time Learning for Data Prefetching. - Lin Jia; James Patrick Mcmahon; Sumanth Gudaparthi; Shreyas Singh; Rajeev Balasubramonian (ASPLOS (3), 2024)

Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference. - Sarabjeet Singh; Shreyas Singh; Sumanth Gudaparthi; Xiong Fan; Rajeev Balasubramonian (SP, 2024)

FLEXPROF: Flexible, Side-Channel-Free Memory Access. - Jarrett Minton; Rajeev Balasubramonian (ASPLOS (2), 2025)