Error tolerance in parallel simulated annealing techniques. - Rajeev Jayaraman; Frederica Darema (ICCD, 1988)

A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. - Rajeev Jayaraman; Rob A. Rutenbar (ICCAD, 1991)

A Novel Predictable Segmented FPGA Routing Architecture. - Emil S. Ochotta; Patrick J. Crotty; Charles R. Erickson; Chih-Tsung Huang; Rajeev Jayaraman; Richard C. Li; Joseph D. Linoff; Luan Ngo; Hy V. Nguyen; Kerry M. Pierce; Douglas P. Wieland; Jennifer Zhuang; et al. (FPGA, 1998)

A Placement Algorithm for FPGA Designs with Multiple I/O Standards. - Jason Helge Anderson; Jim Saunders; Sudip Nag; Chari Madabhushi; Rajeev Jayaraman (FPL, 2000)

Panel: (When) Will FPGAs Kill ASICs? - Rob A. Rutenbar; Max Baron; Thomas Daniel; Rajeev Jayaraman; Zvi Or-Bach; Jonathan Rose; Carl Sechen (DAC, 2001)

Physical design for FPGAs. - Rajeev Jayaraman (ISPD, 2001)

Guest editorial. - Majid Sarrafzadeh; Rajeev Jayaraman (ACM Trans. Design Autom. Electr. Syst., 2002)

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. - Priya Sundararajan; Sridhar Krishnamurthy; Narayanan Vijaykrishnan; Kamal Chaudhary; Rajeev Jayaraman (SoCC, 2006)