Effect of Ge profile design on the performance of an n-p-n SiGe HBT-based analog circuit. - Ankit Kashyap; Rajeev K. Chauhan (Microelectron. J., 2008)

Impact of Ge substrate on drain current of Trigate N-FinFET. - Vimal Kumar Mishra; Rajeev K. Chauhan (ICACCI, 2014)

UWB BPF with Notch Band for Satellite Communication Using Pseudo-Interdigital Structure. - Yatindra Gaurav; Rajeev K. Chauhan (FICTA (1), 2016)

Performance Analysis of Fully Depleted SOI Tapered Body Reduced Source (FD-SOI TBRS) MOSFET for Low Power Digital Applications. - Vimal Kumar Mishra; Rajeev K. Chauhan (FICTA (2), 2016)

Single notch band UWB BPF using square ring resonator. - Yatindra Gaurav; Arvind Kumar Pandey; Rajeev K. Chauhan (RAIT, 2016)

A compact tri-band BPF using meandered ring resonator. - Priyanka Srivastava; Arvind Kumar Pandey; Rajeev K. Chauhan (RAIT, 2016)

Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA. - Mangal Deep Gupta; Rajeev K. Chauhan (IET Comput. Digit. Tech., 2021)

Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box. - Mangal Deep Gupta; Rajeev K. Chauhan (Integr., 2021)

Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2021)

Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic System on FPGA. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2022)

Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network. - Mangal Deep Gupta; Rajeev K. Chauhan; Sandeep Gulia (J. Circuits Syst. Comput., 2023)

Reconfigurable Image Confusion Scheme Using Large Period Pseudorandom Bit Generator Based on Coupled-Variable Input LCG and Clock Divider. - Mangal Deep Gupta; Rajeev K. Chauhan (J. Circuits Syst. Comput., 2024)