Strain for CMOS performance improvement. - Victor Chan; Ken Rim; Meikei Ieong; Sam Yang; Rajeev Malik; Young Way Teh; Min Yang; Qiqing Ouyang (CICC, 2005)

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. - Balaji Jayaraman; Sneha Gupta; Yanli Zhang; Puneet Goyal; Herbert Ho; Rishikesh Krishnan; Sunfei Fang; Sungjae Lee; Douglas Daley; Kevin McStay; Bernhard Wunder; John Barth 001; et al. (ICICDT, 2012)

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM. - Gregory Freeman; Paul Chang; E. R. Engbrecht; K. J. Giewont; David F. Hilscher; M. Lagus; Timothy J. McArdle; B. Morgenfeld; Shreesh Narasimha; James P. Norum; K. A. Nummy; Paul C. Parries; et al. (IBM J. Res. Dev., 2015)