SLIP: a software environment for system level interactive partitioning. - Mark Beardslee; Chuck Kring; Rajeev Murgai; Hamid Savoj; Robert K. Brayton; A. Richard Newton (ICCAD, 1989)

Logic Synthesis for Programmable Gate Arrays. - Rajeev Murgai; Yoshihito Nishizaki; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1990)

On Clustering for Minimum Delay/Area. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Improved Logic Synthesis Algorithms for Table Look Up Architectures. - Rajeev Murgai; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. - Rajeev Murgai; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

An Improved Synthesis Algorithm for Multiplexor-Based PGA's. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Sequential Synthesis for Table Look Up Programmable Gate Arrays. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

Cube-packing and two-level minimization. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1993)

Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1993)

Optimum Functional Decomposition Using Encoding. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Decomposition of logic functions for minimum transition activity. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ED&TC, 1995)

Logic synthesis for a single large look-up table. - Rajeev Murgai; Masahiro Fujita; Fumiyasu Hirose (ICCD, 1995)

Speeding up technology-independent timing optimization by network partitioning. - Rajat Aggarwal; Rajeev Murgai; Masahiro Fujita (ICCAD, 1997)

Some Recent Advances in Software and Hardware Logic Simulation. - Rajeev Murgai; Masahiro Fujita (VLSI Design, 1997)

Using Complementation and Resequencing to Minimize Transitions. - Rajeev Murgai; Masahiro Fujita; Arlindo L. Oliveira (DAC, 1998)

On Reducing Transitions Through Data Modifications. - Rajeev Murgai; Masahiro Fujita (DATE, 1999)

Performance optimization under rise and fall parameters. - Rajeev Murgai (ICCAD, 1999)

On the global fanout optimization problem. - Rajeev Murgai (ICCAD, 1999)

Speeding Up Look-up-Table Driven Logic Simulation. - Rajeev Murgai; Fumiyasu Hirose; Masahiro Fujita (VLSI, 1999)

Efficient Scheduling Techniques for ROBDD Construction. - Rajeev Murgai; Jawahar Jain; Masahiro Fujita (VLSI Design, 1999)

Layout-Driven Area-Constrained Timing Optimization by Net Buffering. - Rajeev Murgai (ICCAD, 2000)

An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. - Arlindo L. Oliveira; Rajeev Murgai (ICCAD, 2000)

Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. - Rajeev Murgai (VLSI Design, 2000)

Efficient global fanout optimization algorithms. - Rajeev Murgai (ASP-DAC, 2001)

Complexity Of Minimum-Delay Gate Resizing. - Supratik Chakraborty; Rajeev Murgai (VLSI Design, 2001)

Layout-Driven Timing Optimization by Generalized De Morgan Transform. - Supratik Chakraborty; Rajeev Murgai (ASP-DAC/VLSI Design, 2002)

PDL: A New Physical Synthesis Methodology. - Toshiyuki Shibuya; Rajeev Murgai; Tadashi Konno; Kazuhiro Emi; Kaoru Kawamura (ISQED, 2003)

On the problem of gate assignment under different rise and fall delays. - Arlindo L. Oliveira; Rajeev Murgai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. - Rajeev Murgai; Subodh M. Reddy; Takashi Miyoshi; Takeshi Horie; Mehdi Baradaran Tahoori (DATE, 2004)

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. - Zhe Wang; Rajeev Murgai; Jaijeet S. Roychowdhury (DATE, 2004)

XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. - Yinghua Li; Rajeev Murgai; Takashi Miyoshi; Ashwini Verma (ICCD, 2004)

Macromodeling of digital libraries for substrate noise analysis. - Zhe Wang; Rajeev Murgai; Jaijeet S. Roychowdhury (ISCAS (5), 2004)

Net Buffering in the Presence of Multiple Timing Views. - Rajeev Murgai (VLSI Design, 2004)

A sliding window scheme for accurate clock mesh analysis. - Hongyu Chen; Chao-Yang Yeh; Gustavo R. Wilke; Subodh M. Reddy; Hoa-van Nguyen; William W. Walker; Rajeev Murgai (ICCAD, 2005)

Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. - Rajeev Murgai (VLSI Design, 2005)

ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. - Zhe Wang; Rajeev Murgai; Jaijeet S. Roychowdhury (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Analyzing timing uncertainty in mesh-based clock architectures. - Subodh M. Reddy; Gustavo R. Wilke; Rajeev Murgai (DATE, 2006)

Clock Distribution Architectures: A Comparative Study. - Chao-Yang Yeh; Gustavo R. Wilke; Hongyu Chen; Subodh M. Reddy; Hoa-van Nguyen; Takashi Miyoshi; William W. Walker; Rajeev Murgai (ISQED, 2006)

Accurate Substrate Noise Analysis Based on Library Module Characterization. - Subodh M. Reddy; Rajeev Murgai (VLSI Design, 2006)

Fast power network analysis with multiple clock domains. - Wanping Zhang; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (ICCD, 2007)

Design and Analysis of "Tree+Local Meshes" Clock Architecture. - Gustavo R. Wilke; Rajeev Murgai (ISQED, 2007)

An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. - Vineet Wason; Rajeev Murgai; William W. Walker (VLSI Design, 2007)

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. - Wanping Zhang; Yi Zhu 002; Wenjian Yu; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Nuriyoki Ito; Chung-Kuan Cheng (DATE, 2008)

Efficient Power Network Analysis Considering Multidomain Clock Gating. - Wanping Zhang; Wenjian Yu; Xiang Hu; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Technology-Dependent Logic Optimization. - Rajeev Murgai (Proc. IEEE, 2015)

SAT-based redundancy removal. - Krishanu Debnath; Rajeev Murgai; Mayank Jain; Janet Olson (DATE, 2018)