Statistical estimation of leakage current considering inter- and intra-die process variation. - Rajeev R. Rao; Ashish Srivastava; David T. Blaauw; Dennis Sylvester (ISLPED, 2003)

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. - Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge (MICRO, 2003)

Leakage-and crosstalk-aware bus encoding for total power reduction. - Harmander Deogun; Rajeev R. Rao; Dennis Sylvester; David T. Blaauw (DAC, 2004)

Parametric yield estimation considering leakage variability. - Rajeev R. Rao; Anirudh Devgan; David T. Blaauw; Dennis Sylvester (DAC, 2004)

Statistical analysis of subthreshold leakage current for VLSI circuits. - Rajeev R. Rao; Ashish Srivastava; David T. Blaauw; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2004)

An efficient surface-based low-power buffer insertion algorithm. - Rajeev R. Rao; David T. Blaauw; Dennis Sylvester; Charles J. Alpert; Sani R. Nassif (ISPD, 2005)

Modeling and Analysis of Parametric Yield under Power and Performance Constraints. - Rajeev R. Rao; David T. Blaauw; Dennis Sylvester; Anirudh Devgan (IEEE Des. Test Comput., 2005)

Bus encoding for total power reduction using a leakage-aware buffer configuration. - Rajeev R. Rao; Harmander Deogun; David T. Blaauw; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2005)

An efficient static algorithm for computing the soft error rates of combinational circuits. - Rajeev R. Rao; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (DATE, 2006)

Soft error reduction in combinational logic using gate resizing and flipflop selection. - Rajeev R. Rao; David T. Blaauw; Dennis Sylvester (ICCAD, 2006)

Logic SER Reduction through Flipflop Redesign. - Vivek Joshi; Rajeev R. Rao; David T. Blaauw; Dennis Sylvester (ISQED, 2006)

Analytical yield prediction considering leakage/performance correlation. - Rajeev R. Rao; Anirudh Devgan; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. - Rajeev R. Rao; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. - Rajeev R. Rao; Vivek Joshi; David T. Blaauw; Dennis Sylvester (ACM Trans. Design Autom. Electr. Syst., 2009)

IBM POWER7+ design for higher frequency at fixed power. - Victor V. Zyuban; Scott A. Taylor; Birger Christensen; A. R. Hall; Christopher J. Gonzalez; Joshua Friedrich; Frances Clougherty; Jon Tetzloff; Rajeev R. Rao (IBM J. Res. Dev., 2013)