Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing. - Pankaj Kumar; Rajender Kumar Sharma (J. Circuits Syst. Comput., 2017)

An Energy Efficient Logic Approach to Implement CMOS Full Adder. - Pankaj Kumar; Rajender Kumar Sharma (J. Circuits Syst. Comput., 2017)

Low power low voltage CMOS full adder cells based on energy-efficient architecture. - Pankaj Kumar; Rajender Kumar Sharma (Int. J. Comput. Appl. Technol., 2018)