Architectural aspects in design and analysis of SOT-based memories. - Rajendra Bishnoi; Mojtaba Ebrahimi; Fabian Oboril; Mehdi Baradaran Tahoori (ASP-DAC, 2014)

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. - Rajendra Bishnoi; Mojtaba Ebrahimi; Fabian Oboril; Mehdi Baradaran Tahoori (DATE, 2014)

Avoiding unnecessary write operations in STT-MRAM for low power implementation. - Rajendra Bishnoi; Fabian Oboril; Mojtaba Ebrahimi; Mehdi Baradaran Tahoori (ISQED, 2014)

Read disturb fault detection in STT-MRAM. - Rajendra Bishnoi; Mojtaba Ebrahimi; Fabian Oboril; Mehdi Baradaran Tahoori (ITC, 2014)

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy. - Fabian Oboril; Rajendra Bishnoi; Mojtaba Ebrahimi; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing. - Rajendra Bishnoi; Fabian Oboril; Mehdi Baradaran Tahoori (ASP-DAC, 2016)

Fault Tolerant Non-Volatile spintronic flip-flop. - Rajendra Bishnoi; Fabian Oboril; Mehdi Baradaran Tahoori (DATE, 2016)

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing. - Anteneh Gebregiorgis; Saman Kiamehr; Fabian Oboril; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2016)

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices. - Rajendra Bishnoi; Fabian Oboril; Mehdi Baradaran Tahoori (ACM Great Lakes Symposium on VLSI, 2016)

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. - Fabian Oboril; Fazal Hameed; Rajendra Bishnoi; Ali Ahari; Helia Naeimi; Mehdi Baradaran Tahoori (ISLPED, 2016)

Layout-Based Modeling and Mitigation of Multiple Event Transients. - Mojtaba Ebrahimi; Hossein Asadi 001; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. - Guillaume Prenat; Kotb Jabeur; Pierre Vanhauwaert; Gregory di Pendina; Fabian Oboril; Rajendra Bishnoi; Mojtaba Ebrahimi; Nathalie Lamard; Olivier Boulle; Kevin Garello; Juergen Langer; Berthold Ocker; et al. (IEEE Trans. Multi Scale Comput. Syst., 2016)

Self-Timed Read and Write Operations in STT-MRAM. - Rajendra Bishnoi; Fabian Oboril; Mojtaba Ebrahimi; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2016)

VAET-STT: A variation aware estimator tool for STT-MRAM based memories. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mohammad Saber Golanbari; Fabian Oboril; Mehdi Baradaran Tahoori (DATE, 2017)

Opportunistic write for fast and reliable STT-MRAM. - Nour Sayed; Mojtaba Ebrahimi; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2017)

Exploiting STT-MRAM for approximate computing. - Nour Sayed; Fabian Oboril; Azadeh Shirvanian; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ETS, 2017)

Architecting SOT-RAM Based GPU Register File. - Sparsh Mittal; Rajendra Bishnoi; Fabian Oboril; Haonan Wang; Mehdi Baradaran Tahoori; Adwait Jog; Jeffrey S. Vetter (ISVLSI, 2017)

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Pascal Nouet; Rui Ma; Martin Kreißig; Frank Ellinger; et al. (ISVLSI, 2017)

Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache. - Nour Sayed; Fabian Oboril; Rajendra Bishnoi; Mehdi Baradaran Tahoori (VTS, 2017)

Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. - Rajendra Bishnoi; Fabian Oboril; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Reliable Low-Power High Performance Spintronic Memories - Rajendra Bishnoi (2017)

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. - Nour Sayed; Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ASP-DAC, 2018)

Spintronic normally-off heterogeneous system-on-chip design. - Anteneh Gebregiorgis; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2018)

Multi-bit non-volatile spintronic flip-flop. - Christopher Münch; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2018)

Parametric failure modeling and yield analysis for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2018)

A cross-layer adaptive approach for performance and power optimization in STT-MRAM. - Nour Sayed; Rajendra Bishnoi; Fabian Oboril; Mehdi Baradaran Tahoori (DATE, 2018)

Using multifunctional standardized stack as universal spintronic technology for IoT. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Abdoulaye Gamatié; Pascal Nouet; Frederic Ouattara; Gilles Sassatelli; et al. (DATE, 2018)

Design and evaluation of physical unclonable function for inorganic printed electronics. - Ahmet Turan Erozan; Mohammad Saber Golanbari; Rajendra Bishnoi; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (ISQED, 2018)

Reliable memory PUF design for low-power applications. - Mohammad Saber Golanbari; Saman Kiamehr; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ISQED, 2018)

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Grigor Tshagharyan; Hayk T. Grigoryan; Gurgen Harutyunyan; Yervant Zorian (ITC, 2018)

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. - Grigor Tshagharyan; Gurgen Harutyunyan; Yervant Zorian; Anteneh Gebregiorgis; Mohammad Saber Golanbari; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ITC, 2018)

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mohammad Saber Golanbari; Fabian Oboril; Fazal Hameed; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication. - Ahmet Turan Erozan; Gabriel Cadilha Marques; Mohammad Saber Golanbari; Rajendra Bishnoi; Simone Dehm; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Reliable in-memory neuromorphic computing using spintronics. - Christopher Münch; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ASP-DAC, 2019)

Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning. - Ahmet Turan Erozan; Rajendra Bishnoi; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (DATE, 2019)

Predictive Modeling and Design Automation of Inorganic Printed Electronics. - Farhan Rasheed; Michael Hefenbrock; Rajendra Bishnoi; Michael Beigl; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (DATE, 2019)

Variation-aware Fault Modeling and Test Generation for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Hayk T. Grigoryan; Grigor Tshagharyan (IOLTS, 2019)

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2019)

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. - Anteneh Gebregiorgis; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design. - Nour Sayed; Longfei Mao; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ACM Trans. Design Autom. Electr. Syst., 2019)

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. - Samir Ben Dodo; Rajendra Bishnoi; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. - Nour Sayed; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories. - Christopher Münch; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ASP-DAC, 2020)

Dynamic Faults based Hardware Trojan Design in STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Arunkumar Vijayan; Mehdi Baradaran Tahoori (DATE, 2020)

A Universal Spintronic Technology based on Multifunctional Standardized Stack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Lionel Torres; Sophiane Senni; Guillaume Patrigeon; Pascal Benoit; Gregory di Pendina; Guillaume Prenat (DATE, 2020)

Testing Scouting Logic-Based Computation-in-Memory Architectures. - Moritz Fieback; Surya Nagarajan; Rajendra Bishnoi; Mehdi B. Tahoori; Mottaqiallah Taouil; Said Hamdioui (ETS, 2020)

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi B. Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2020)

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. - Rajendra Bishnoi; Lizhou Wu; Moritz Fieback; Christopher Münch; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori; Ying Wang 001; Huawei Li 001; Said Hamdioui (VTS, 2020)

Mitigating Read Failures in STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (VTS, 2020)

Crossover-aware Placement and Routing for Inkjet Printed Circuits. - Farhan Rasheed; Michael Hefenbrock; Rajendra Bishnoi; Michael Beigl; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (ACM J. Emerg. Technol. Comput. Syst., 2020)

Approximate Spintronic Memories. - Nour Sayed; Rajendra Bishnoi; Mehdi B. Tahoori (ACM J. Emerg. Technol. Comput. Syst., 2020)

Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks. - Samir Ben Dodo; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology. - Ahmet Turan Erozan; Guan Ying Wang; Rajendra Bishnoi; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit. - Ahmet Turan Erozan; Dennis D. Weller; Farhan Rasheed; Rajendra Bishnoi; Jasmin Aghassi-Hagmann; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. - Sumit Diware; Anteneh Gebregiorgis; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (AICAS, 2021)

Low-Power Memristor-Based Computing for Edge-AI Applications. - Abhairaj Singh; Sumit Diware; Anteneh Gebregiorgis; Rajendra Bishnoi; Francky Catthoor; Rajiv V. Joshi; Said Hamdioui (ISCAS, 2021)

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. - Patrick Girard 001; Yuanqing Cheng; Arnaud Virazel; Wei Zhao 010; Rajendra Bishnoi; Mehdi B. Tahoori (Proc. IEEE, 2021)

SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. - Abhairaj Singh; Muath Abu Lebdeh; Anteneh Gebregiorgis; Rajendra Bishnoi; Rajiv V. Joshi; Said Hamdioui (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. - Abhairaj Singh; Mahdi Zahedi; Taha Shahroodi; Mohit Gupta 004; Anteneh Gebregiorgis; Manu Komalan; Rajiv V. Joshi; Francky Catthoor; Rajendra Bishnoi; Said Hamdioui (AICAS, 2022)

Referencing-in-Array Scheme for RRAM-based CIM Architecture. - Abhairaj Singh; Rajendra Bishnoi; Rajiv V. Joshi; Said Hamdioui (DATE, 2022)

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. - Abhairaj Singh; Moritz Fieback; Rajendra Bishnoi; Filip Bradaric; Anteneh Gebregiorgis; Rajiv V. Joshi; Said Hamdioui (ITC, 2022)

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs. - Anteneh Gebregiorgis; Abhairaj Singh; Sumit Diware; Rajendra Bishnoi; Said Hamdioui (VLSI-SoC, 2022)

CONVOLVE: Smart and seamless design of smart edge processors. - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Frank K. Zenke; et al. (CoRR, 2022)

Defects, Fault Modeling, and Test Development Framework for RRAMs. - Moritz Fieback; Guilherme Cardoso Medeiros; Lizhou Wu; Hassen Aziza; Rajendra Bishnoi; Mottaqiallah Taouil; Said Hamdioui (ACM J. Emerg. Technol. Comput. Syst., 2022)

A Survey on Memory-centric Computer Architectures. - Anteneh Gebregiorgis; Hoang Anh Du Nguyen; Jintao Yu; Rajendra Bishnoi; Mottaqiallah Taouil; Francky Catthoor; Said Hamdioui (ACM J. Emerg. Technol. Comput. Syst., 2022)

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. - Mahta Mayahinia; Abhairaj Singh; Christopher Bengel; Stefan Wiefels; Muath Abu Lebdeh; Stephan Menzel; Dirk J. Wouters; Anteneh Gebregiorgis; Rajendra Bishnoi; Rajiv V. Joshi; Said Hamdioui (ACM J. Emerg. Technol. Comput. Syst., 2022)

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices. - Christopher Bengel; Johannes Mohr; Stefan Wiefels; Abhairaj Singh; Anteneh Gebregiorgis; Rajendra Bishnoi; Said Hamdioui; Rainer Waser; Dirk J. Wouters; Stephan Menzel (Neuromorph. Comput. Eng., 2022)

Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. - Sumit Diware; Anteneh Gebregiorgis; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (AICAS, 2023)

A 115.1 TOPS/W, 12.1 TOPS/mm2 Computation-in-Memory using Ring-Oscillator based ADC for Edge AI. - Abhairaj Singh; Rajendra Bishnoi; Ali Kaichouhi; Sumit Diware; Rajiv V. Joshi; Said Hamdioui (AICAS, 2023)

Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. - Mohammad Amin Yaldagard; Sumit Diware; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (AICAS, 2023)

PetaOps/W edge-AI $ mu$ Processors: Myth or reality? - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Friedemann Zenke; et al. (DATE, 2023)

Memristor-Based Lightweight Encryption. - Muhammad Ali Siddiqi; Jan Andrés Galvan Hernández; Anteneh Gebreziorgis; Rajendra Bishnoi; Christos Strydis; Said Hamdioui; Mottaqiallah Taouil (DSD, 2023)

Dependability of Future Edge-AI Processors: Pandora's Box. - Manil Dev Gomony; Anteneh Gebregiorgis; Moritz Fieback; Marc Geilen; Sander Stuijk; Jan Richter-Brockmann; Rajendra Bishnoi; Sven Argo; Lara Arche Andradas; Tim Güneysu; Mottaqiallah Taouil; Henk Corporaal; et al. (ETS, 2023)

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. - Rajendra Bishnoi; Sumit Diware; Anteneh Gebregiorgis; Simon Thomann; Sara Mannaa; Bastien Deveautour; Cédric Marchand 002; Alberto Bosio; Damien Deleruyelle; Ian O'Connor; Hussam Amrouch; Said Hamdioui (ICM, 2023)

On the Reliability of RRAM-Based Neural Networks. - Hassen Aziza; Cristian Zambelli; Said Hamdioui; Sumit Diware; Rajendra Bishnoi; Anteneh Gebregiorgis (VLSI-SoC, 2023)

Severity-Based Hierarchical ECG Classification Using Neural Networks. - Sumit Diware; Sudeshna Dash; Anteneh Gebregiorgis; Rajiv V. Joshi; Christos Strydis; Said Hamdioui; Rajendra Bishnoi (IEEE Trans. Biomed. Circuits Syst., 2023)

Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. - Sumit Diware; Abhairaj Singh; Anteneh Gebregiorgis; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (IEEE Trans. Emerg. Top. Comput. Intell., 2023)

Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. - Sumit Diware; Mohammad Amin Yaldagard; Anteneh Gebregiorgis; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (AICAS, 2024)

A Lightweight Architecture for Real-Time Neuronal-Spike Classification. - Muhammad Ali Siddiqi; David Vrijenhoek; Lennart P. L. Landsmeer; Job van der Kleij; Anteneh Gebregiorgis; Vincenzo Romano; Rajendra Bishnoi; Said Hamdioui; Christos Strydis (CF, 2024)

Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning. - Lucas Huijbregts; Hsiao-Hsuan Liu; Paul Detterer; Said Hamdioui; Amirreza Yousefzadeh; Rajendra Bishnoi (DAC, 2024)

Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks. - Sumit Diware; Mohammad Amin Yaldagard; Rajendra Bishnoi (ICCAD, 2024)

Real-Time Supervised Spiking Neural Network for Cerebellar Purkinje Cells Spike Detection and Classification. - Alireza Raisiardali; Muhammad Ali Siddiqi; Christos Strydis; Said Hamdioui; Dante Gabriel Muratore; Rajendra Bishnoi (ICONS, 2024)

Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. - Sumit Diware; Koteswararao Chilakala; Rajiv V. Joshi; Said Hamdioui; Rajendra Bishnoi (IEEE Access, 2024)

Memristor-Based Lightweight Encryption. - Muhammad Ali Siddiqi; Jan Andrés Galvan Hernández; Anteneh Gebregiorgis; Rajendra Bishnoi; Christos Strydis; Said Hamdioui; Mottaqiallah Taouil (CoRR, 2024)

Multi-Partner Project: A Deep Learning Platform Targeting Embedded Hardware for Edge-AI Applications (NEUROKIT2E). - Rajendra Bishnoi; Mohammad Amin Yaldagard; Said Hamdioui; Kanishkan Vadivel; Manolis Sifalakis; Nicolas Daniel Rodriguez; Pedro Julián; Lothar Ratschbacher; Maen Mallah; Yogesh Ramesh Patil; Rashid Ali; Fabian Chersi (DATE, 2025)

C3CIM: Constant Column Current Memristor-Based Computation-in-Memory Micro-Architecture. - Yashvardhan Biyani; Rajendra Bishnoi; Theofilos Spyrou; Said Hamdioui (DATE, 2025)

Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture Using Spiking Neural Network. - Sumit Diware; Yingzhou Dong; Mohammad Amin Yaldagard; Said Hamdioui; Rajendra Bishnoi (DATE, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

In-Field Monitoring and Preventing Read Disturb Faults in RRAMs. - Hanzhi Xun; Moritz Fieback; Sicong Yuan; Changhao Wang; Erbing Hua; Hassen Aziza; Leticia Bolzani Poehls; Riccardo Cantoro; Rajendra Bishnoi; Mottaqiallah Taouil; Said Hamdioui (ETS, 2025)