PAPR Reduction for OFDM Scheme by New Partial Transmit Sequence Technique in Wireless Communication Systems. - Pankaj Kumar Sharma; Rajendra Kumar Nagaria; T. N. Sharma (CICSyN, 2009)

On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop. - Rajendra Kumar Nagaria; Rakesh Kumar Singh; Subodh Wairya (J. Circuits Syst. Comput., 2010)

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. - Subodh Wairya; Rajendra Kumar Nagaria; Sudarshan Tiwari (VLSI Design, 2012)

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic. - Shipra Upadhyay; Rajendra Kumar Nagaria; Ram Awadh Mishra (VLSI Design, 2013)

A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies. - Sankit R. Kassa; Rajendra Kumar Nagaria (ICCCT, 2015)

An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata. - Sankit R. Kassa; Rajendra Kumar Nagaria (J. Low Power Electron., 2016)

A Novel Design for 4-Bit Code Converters in Quantum Dot Cellular Automata. - Sankit R. Kassa; Rajendra Kumar Nagaria (J. Low Power Electron., 2017)

A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits. - Ankur Kumar; Rajendra Kumar Nagaria (Integr., 2018)

Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique. - Avaneesh K. Dubey; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2018)

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load. - Avaneesh K. Dubey; Rajendra Kumar Nagaria (Microelectron. J., 2018)

Energy efficient neoteric design of a 3-input Majority Gate with its implementation and physical proof in Quantum dot Cellular Automata. - Sankit R. Kassa; Rajendra Kumar Nagaria; R. Karthik 002 (Nano Commun. Networks, 2018)

Energy Efficient Angle based Route Selection in 3D Wireless Sensor Networks. - Naveen Kumar Gupta; Rama Shankar Yadav; Rajendra Kumar Nagaria (SICE, 2019)

Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect. - Avaneesh K. Dubey; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2019)

A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing. - Pratosh Kumar Pal; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2019)

Anchor Based Geographical Routing in WSN. - Naveen Kumar Gupta; Rama Shankar Yadav; Rajendra Kumar Nagaria (ICSCA, 2020)

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load. - Pratosh Kumar Pal; Rajendra Kumar Nagaria (Integr., 2020)

3D geographical routing protocols in wireless ad hoc and sensor networks: an overview. - Naveen Kumar Gupta; Rama Shankar Yadav; Rajendra Kumar Nagaria (Wirel. Networks, 2020)

An Angular 3D Path Selection Protocol in Wireless Sensor Networks. - Naveen Kumar Gupta; Rama Shankar Yadav; Rajendra Kumar Nagaria; Deepak Gupta (Open Comput. Sci., 2021)

Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications. - Vikrant Varshney; Avaneesh K. Dubey; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2021)

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic. - Ankur Kumar; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2022)

Reduction of variation and leakage in wide fan-in OR Logic domino gate. - Ankur Kumar; Rajendra Kumar Nagaria (Integr., 2023)

Anchor-based void detouring routing protocol in three dimensional IoT networks. - Naveen Kumar Gupta; Rama Shankar Yadav; Rajendra Kumar Nagaria; Deepak Gupta; Achyut Mani Tripathi; Om Jee Pandey (Comput. Networks, 2023)

Self Organized Anchor Group based Routing Protocol for IoT Initial Setup. - Naveen Kumar Gupta; Apeksha Aggarwal; Rama Shankar Yadav; Rajendra Kumar Nagaria (COMSNETS, 2025)

Energy efficient anchor zone based routing protocol for IoT networks. - Naveen Kumar Gupta; Garima; Rama Shankar Yadav; Rajendra Kumar Nagaria (Comput. Electr. Eng., 2025)

A low power noise tolerant wide fan-in OR logic domino gate. - Ankur Kumar; Naman Garg; Rajendra Kumar Nagaria (Integr., 2025)

Design Techniques for High-Speed and Low Power SAR ADC: A Review. - Vikas Tiwari; Rajendra Kumar Nagaria (J. Circuits Syst. Comput., 2025)