A Constrained Genetic Algorithm for Efficient Dimensionality Reduction for Pattern Classification. - Rajesh Chandrasekhara Panicker; Sadasivan Puthusserypady (CIS, 2007)

Asynchronous P300 BCI: SSVEP-based control state detection. - Rajesh Chandrasekhara Panicker; Sadasivan Puthusserypady; Ananda P. Pryana; Ying Sun 001 (EUSIPCO, 2010)

Adaptation in P300 Brain-Computer Interfaces: A Two-Classifier Cotraining Approach. - Rajesh Chandrasekhara Panicker; Sadasivan Puthusserypady; Ying Sun 001 (IEEE Trans. Biomed. Eng., 2010)

An Asynchronous P300 BCI With SSVEP-Based Control State Detection. - Rajesh Chandrasekhara Panicker; Sadasivan Puthusserypady; Ying Sun 001 (IEEE Trans. Biomed. Eng., 2011)

Development of an FPGA-based real-time P300 speller. - Kanav Khurana; Pooja Gupta; Rajesh Chandrasekhara Panicker; Akash Kumar 001 (FPL, 2012)

Project-Based Learning in Embedded Systems Education Using an FPGA Platform. - Akash Kumar 001; Shakith Fernando; Rajesh Chandrasekhara Panicker (IEEE Trans. Educ., 2013)

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. - Yi Sheng Chong; Rakshith Harish; Rajesh Chandrasekhara Panicker; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2024)