An automatic test pattern generation program for large ASICs. - Dick L. Liu; Rajesh Galivanche; Charlie C. Hsu (ICCD, 1989)

Test challenges in nanometer technologies. - Sandip Kundu; Sanjay Sengupta; Rajesh Galivanche (ETW, 2000)

Test Challenges in Nanometer Technologies. - Sandip Kundu; Sujit T. Zachariah; Sanjay Sengupta; Rajesh Galivanche (J. Electron. Test., 2001)

Circuit and Platform Design Challenges in Technologies beyond 90nm. - Bill Grundmann; Rajesh Galivanche; Sandip Kundu (DATE, 2003)

Trends in manufacturing test methods and their implications. - Sandip Kundu; T. M. Mak; Rajesh Galivanche (ITC, 2004)

Is the concern for soft-error overblown? - Rajesh Galivanche (ITC, 2005)

Session Abstract. - Rajesh Galivanche; Bob Gottlieb (VTS, 2006)

Test Roles in Diagnosis and Silicon Debug. - Anis Uzzaman; Fidel Muradali; Takashi Aikyo; Robert C. Aitken; Tom Jackson; Rajesh Galivanche; Takeshi Onodera (ATS, 2007)

Testing in the year 2020. - Rajesh Galivanche; Rohit Kapur; Antonio Rubio 001 (DATE, 2007)

A low-cost concurrent error detection technique for processor control logic. - Ramtilak Vemu; Abhijit Jas; Jacob A. Abraham; Srinivas Patil; Rajesh Galivanche (DATE, 2008)

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. - Cecilia Metra; Daniele Rossi 001; Martin Omaña 001; Abhijit Jas; Rajesh Galivanche (ETS, 2008)

The Challenges of Nanotechnology and Gigacomplexity. - Gadi Singer; Rajesh Galivanche; Srinivas Patil; Mike Tripp (IEEE Des. Test Comput., 2009)

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. - Daniele Rossi 001; Martin Omaña 001; Gianluca Berghella; Cecilia Metra; Abhijit Jas; Chandra Tirumurti; Rajesh Galivanche (Conf. Computing Frontiers, 2010)

Bridging pre-silicon verification and post-silicon validation. - Amir Nahir; Avi Ziv; Rajesh Galivanche; Alan J. Hu; Miron Abramovici; Albert Camilleri; Bob Bentley; Harry Foster; Valeria Bertacco; Shakti Kapoor (DAC, 2010)

Path coverage based functional test generation for processor marginality validation. - Suriyaprakash Natarajan; Arun Krishnamachary; Eli Chiprout; Rajesh Galivanche (ITC, 2010)

Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. - Cecilia Metra; Rajesh Galivanche (IEEE Trans. Computers, 2011)

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. - Michail Maniatakos; Chandrasekharan Tirumurti; Rajesh Galivanche; Yiorgos Makris (IEEE Trans. Computers, 2012)

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. - Daniele Rossi 001; Martin Omaña 001; G. Garrammone; Cecilia Metra; Abhijit Jas; Rajesh Galivanche (J. Electron. Test., 2013)

Power droop reduction during Launch-On-Shift scan-based logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (DFT, 2014)

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Edda Beniamino; Cecilia Metra; Chandrasekharan Tirumurti; Rajesh Galivanche (IEEE Trans. Computers, 2016)

New Approaches for Power Binning of High Performance Microprocessors. - Martin Omaña 001; Marco Padovani; Kreshnik Veliu; Cecilia Metra; Juergen Alt; Rajesh Galivanche (IEEE Trans. Computers, 2017)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. - Martin Omaña 001; Daniele Rossi 001; Filippo Fuzzi; Cecilia Metra; Chandra Tirumurti; Rajesh Galivanche (IEEE Trans. Very Large Scale Integr. Syst., 2017)